Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8aba6143 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'arm-soc/for-4.13/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64 

This pull request contains Broadcom ARM64-based SoCs Device Tree changes for
4.13. Please note the following from Eric:

I've based this summary on the bcm2835-dt-next tag, to clarify what's in this
patch series, but it does require being careful since it involves a cross-merge
between branches.

- Anup documents the Broadcom Stingray binding, common clocks, adds initial
  support for the Stingray DTSI and DTS files and adds support for the PL022,
  PL330 and SP805

- Sandeep adds the clock nodes to the Stingray Device Tree nodes

- Pramod adds support for the NAND, pinctrl, GPIO to the Stingray Device Tree nodes

- Oza adds I2C Device Tree nodes to the Stingray DTSes

- Srinath adds PWM and SDHCI Device Tree nodes for the Stingray SoC

- Ravijeta adds support for the USB Dual Role PHY on Northstar 2

- Gerd starts adding references to the sdhost and sdhci controllers, and then
  switches the sdcard to to use the SDHOST (faster than SDHCI)

- Stefan defines the BCM2837 thermal coefficients in order for the Raspberry Pi
  thermal driver to work correctly

* tag 'arm-soc/for-4.13/devicetree-arm64' of http://github.com/Broadcom/stblinux

:
  arm64: dts: NS2: Add USB DRD PHY device tree node
  ARM64: dts: bcm2837: Define CPU thermal coefficients
  arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC
  arm64: dts: Add PL022, PL330 and SP805 DT nodes for Stingray
  arm64: dts: Add I2C DT nodes for Stingray SoC
  arm64: dts: Add GPIO DT nodes for Stingray SOC
  arm64: dts: Add pinctrl DT nodes for Stingray SOC
  arm64: dts: Add NAND DT nodes for Stingray SOC
  arm64: dts: Add clock DT nodes for Stingray SOC
  arm64: dts: Initial DTS files for Broadcom Stingray SOC
  dt-bindings: clk: Extend binding doc for Stingray SOC
  dt-bindings: bcm: Add Broadcom Stingray bindings document
  ARM: dts: bcm283x: switch from &sdhci to &sdhost
  arm64: dts: bcm2837: add &sdhci and &sdhost
  ARM: dts: bcm283x: Add CPU thermal zone with 1 trip point
  ARM: dts: Add devicetree for the Raspberry Pi 3, for arm32 (v6)

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents d828e978 39b1aae7

Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt

0 → 100644
+12 −0
Original line number Diff line number Diff line 
Broadcom Stingray device tree bindings

------------------------------------------------



Boards with Stingray shall have the following properties:



Required root node property:



Stingray Combo SVK board

compatible = "brcm,bcm958742k", "brcm,stingray";



Stingray SST100 board

compatible = "brcm,bcm958742t", "brcm,stingray";

Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt

+76 −0
Original line number Diff line number Diff line
@@ -219,3 +219,79 @@ BCM63138 
--------

PLL and leaf clock compatible strings for BCM63138 are:

    "brcm,bcm63138-armpll"



Stingray

-----------

PLL and leaf clock compatible strings for Stingray are:

    "brcm,sr-genpll0"

    "brcm,sr-genpll1"

    "brcm,sr-genpll2"

    "brcm,sr-genpll3"

    "brcm,sr-genpll4"

    "brcm,sr-genpll5"

    "brcm,sr-genpll6"



    "brcm,sr-lcpll0"

    "brcm,sr-lcpll1"

    "brcm,sr-lcpll-pcie"





The following table defines the set of PLL/clock index and ID for Stingray.

These clock IDs are defined in:

    "include/dt-bindings/clock/bcm-sr.h"



    Clock		Source		Index	ID

    ---			-----		-----	---------

    crystal		N/A		N/A	N/A

    crmu_ref25m		crystal		N/A	N/A



    genpll0		crystal		0	BCM_SR_GENPLL0

    clk_125m		genpll0		1	BCM_SR_GENPLL0_125M_CLK

    clk_scr		genpll0		2	BCM_SR_GENPLL0_SCR_CLK

    clk_250		genpll0		3	BCM_SR_GENPLL0_250M_CLK

    clk_pcie_axi	genpll0		4	BCM_SR_GENPLL0_PCIE_AXI_CLK

    clk_paxc_axi_x2	genpll0		5	BCM_SR_GENPLL0_PAXC_AXI_X2_CLK

    clk_paxc_axi	genpll0		6	BCM_SR_GENPLL0_PAXC_AXI_CLK



    genpll1		crystal		0	BCM_SR_GENPLL1

    clk_pcie_tl		genpll1		1	BCM_SR_GENPLL1_PCIE_TL_CLK

    clk_mhb_apb		genpll1		2	BCM_SR_GENPLL1_MHB_APB_CLK



    genpll2		crystal		0	BCM_SR_GENPLL2

    clk_nic		genpll2		1	BCM_SR_GENPLL2_NIC_CLK

    clk_ts_500_ref	genpll2		2	BCM_SR_GENPLL2_TS_500_REF_CLK

    clk_125_nitro	genpll2		3	BCM_SR_GENPLL2_125_NITRO_CLK

    clk_chimp		genpll2		4	BCM_SR_GENPLL2_CHIMP_CLK

    clk_nic_flash	genpll2		5	BCM_SR_GENPLL2_NIC_FLASH



    genpll3		crystal		0	BCM_SR_GENPLL3

    clk_hsls		genpll3		1	BCM_SR_GENPLL3_HSLS_CLK

    clk_sdio		genpll3		2	BCM_SR_GENPLL3_SDIO_CLK



    genpll4		crystal		0	BCM_SR_GENPLL4

    ccn			genpll4		1	BCM_SR_GENPLL4_CCN_CLK

    clk_tpiu_pll	genpll4		2	BCM_SR_GENPLL4_TPIU_PLL_CLK

    noc_clk		genpll4		3	BCM_SR_GENPLL4_NOC_CLK

    clk_chclk_fs4	genpll4		4	BCM_SR_GENPLL4_CHCLK_FS4_CLK

    clk_bridge_fscpu	genpll4		5	BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK





    genpll5		crystal		0	BCM_SR_GENPLL5

    fs4_hf_clk		genpll5		1	BCM_SR_GENPLL5_FS4_HF_CLK

    crypto_ae_clk	genpll5		2	BCM_SR_GENPLL5_CRYPTO_AE_CLK

    raid_ae_clk		genpll5		3	BCM_SR_GENPLL5_RAID_AE_CLK



    genpll6		crystal		0	BCM_SR_GENPLL6

    48_usb		genpll6		1	BCM_SR_GENPLL6_48_USB_CLK



    lcpll0		crystal		0	BCM_SR_LCPLL0

    clk_sata_refp 	lcpll0		1	BCM_SR_LCPLL0_SATA_REFP_CLK

    clk_sata_refn	lcpll0		2	BCM_SR_LCPLL0_SATA_REFN_CLK

    clk_usb_ref		lcpll0		3	BCM_SR_LCPLL0_USB_REF_CLK

    sata_refpn		lcpll0		3	BCM_SR_LCPLL0_SATA_REFPN_CLK



    lcpll1		crystal		0	BCM_SR_LCPLL1

    wan 		lcpll1		1	BCM_SR_LCPLL0_WAN_CLK



    lcpll_pcie		crystal		0	BCM_SR_LCPLL_PCIE

    pcie_phy_ref 	lcpll1		1	BCM_SR_LCPLL_PCIE_PHY_REF_CLK

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ 
	bcm2835-rpi-b-plus.dtb \

	bcm2835-rpi-a-plus.dtb \

	bcm2836-rpi-2-b.dtb \

	bcm2837-rpi-3-b.dtb \

	bcm2835-rpi-zero.dtb

dtb-$(CONFIG_ARCH_BCM_5301X) += \

	bcm4708-asus-rt-ac56u.dtb \

arch/arm/boot/dts/bcm2835-rpi.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -65,13 +65,13 @@ 
&sdhci {

	pinctrl-names = "default";

	pinctrl-0 = <&emmc_gpio48>;

	status = "okay";

	bus-width = <4>;

};



&sdhost {

	pinctrl-names = "default";

	pinctrl-0 = <&sdhost_gpio48>;

	status = "okay";

	bus-width = <4>;

};

arch/arm/boot/dts/bcm2835.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -24,6 +24,10 @@ 
	};

};



&cpu_thermal {

	coefficients = <(-538)	407000>;

};



/* enable thermal sensor with the correct compatible property set */

&thermal {

	compatible = "brcm,bcm2835-thermal";