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Commit 8a0d40c0 authored by Dhaval Patel's avatar Dhaval Patel
Browse files

clk: qcom: dispcc-sm8150: disable byte0/1 clock gate 



Disable byte0 and byte1 clock gate for sm8150 target
on display clock controller block.

Change-Id: I4c9c1a247379ee3f0c36a7feab3c468780f444f7
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 1dbd9790

drivers/clk/qcom/dispcc-sm8150.c

+1 −1
Original line number Diff line number Diff line
@@ -1522,7 +1522,7 @@ static int disp_cc_sm8150_probe(struct platform_device *pdev) 
	clk_trion_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);



	/* Enable clock gating for DSI and MDP clocks */

	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x7f0, 0x7f0);

	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x670, 0x670);



	ret = qcom_cc_really_probe(pdev, &disp_cc_sm8150_desc, regmap);

	if (ret) {