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Commit 89822ecf authored Jul 25, 2019 by Jayadev K Committed by Gerrit - the friendly Code Review server Jul 30, 2019

ARM: dts: qcom: Add new properties for HS-I2S node



Adding 'bit-clock-hz' and 'interrupt-interval-ms' properties in
the HS-I2S device node in order to calculate periodic length of
the DMA buffer.

Change-Id: I5c7bea30fe197071f07205d5be41682bf8723ef9
Signed-off-by: Jayadev K <jayak@codeaurora.org>

parent bacc0533

Documentation/devicetree/bindings/sound/qcom,hsi2s.txt

+2 −0

Original line number	Diff line number	Diff line
		@@ -15,6 +15,8 @@ Required properties:
		- interrupts : Interrupt number used by this interface
		- clocks : Core clocks used by this interface
		- clock-names : Clock names for each core clock
		- bit-clock-hz : Default bit clock frequency in hertz
		- interrupt-interval-ms : Default interrupt interval in milliseconds

		* HS-I2S interface nodes

arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -64,6 +64,8 @@
		clock-names = "core_clk", "wr0_mem_clk",
		"wr1_mem_clk", "wr2_mem_clk",
		"csr_hclk";
		bit-clock-hz = <20000000>;
		interrupt-interval-ms = <10>;

		sdr0: qcom,hs0_i2s {
		compatible = "qcom,hsi2s-interface";

arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -57,6 +57,8 @@
		clock-names = "core_clk", "wr0_mem_clk",
		"wr1_mem_clk", "wr2_mem_clk",
		"csr_hclk";
		bit-clock-hz = <20000000>;
		interrupt-interval-ms = <10>;

		sdr0: qcom,hs0_i2s {
		compatible = "qcom,hsi2s-interface";

arch/arm64/boot/dts/qcom/sa8155.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -506,6 +506,8 @@
		<0x17080000 0xE000>;
		reg-names = "lpa_if", "lpass_tcsr";
		interrupts = <GIC_SPI 267 0>;
		bit-clock-hz = <20000000>;
		interrupt-interval-ms = <10>;

		sdr0: qcom,hs0_i2s {
		compatible = "qcom,hsi2s-interface";