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Commit 897244f1 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Enable Adaptive Clock Distribution on A640"

parents 2f44eb8e cd16e4b3

Documentation/devicetree/bindings/gpu/adreno-pwrlevels.txt

+6 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. GPU powerlevels 


Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins)

can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a

voltage, bus, and bandwitdh level.

voltage, bus, bandwidth level, and a DVM value.



- qcom,gpu-pwrlevel-bins:	Contains one or more qcom,gpu-pwrlevels sets
@@ -28,3 +28,8 @@ Properties: 
				settings)

- qcom,bus-min			Minimum bus level to set for the power level

- qcom,bus-max			maximum bus level to set for the power level

- qcom,dvm-val:			Value that is used as a register setting for

				the ACD power feature. It helps determine the

				threshold for when ACD activates. 0xFFFFFFFF

				is the default value, and the setting where

				ACD will never activate.

arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -215,6 +215,7 @@ 
				qcom,bus-freq = <12>;

				qcom,bus-min = <10>;

				qcom,bus-max = <12>;

				qcom,dvm-val = <0xffffffff>;

			};



			qcom,gpu-pwrlevel@1 {
@@ -223,6 +224,7 @@ 
				qcom,bus-freq = <10>;

				qcom,bus-min = <9>;

				qcom,bus-max = <11>;

				qcom,dvm-val = <0xffffffff>;

			};
@@ -232,6 +234,7 @@ 
				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

				qcom,dvm-val = <0xffffffff>;

			};



			qcom,gpu-pwrlevel@3 {
@@ -240,6 +243,7 @@ 
				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

				qcom,dvm-val = <0xffffffff>;

			};
@@ -249,6 +253,7 @@ 
				qcom,bus-freq = <5>;

				qcom,bus-min = <5>;

				qcom,bus-max = <7>;

				qcom,dvm-val = <0xffffffff>;

			};



			qcom,gpu-pwrlevel@5 {
@@ -257,6 +262,7 @@ 
				qcom,bus-freq = <4>;

				qcom,bus-min = <3>;

				qcom,bus-max = <5>;

				qcom,dvm-val = <0xffffffff>;

			};



			qcom,gpu-pwrlevel@6 {
@@ -265,6 +271,7 @@ 
				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

				qcom,dvm-val = <0xffffffff>;

			};

		};

	};
@@ -330,6 +337,10 @@ 
		clock-names = "gmu_clk", "cxo_clk", "axi_clk",

				"memnoc_clk", "gpu_cc_ahb";



		/* AOP mailbox for sending ACD enable and disable messages */

		mboxes = <&qmp_aop 0>;

		mbox-names = "aop";



		qcom,gmu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

drivers/gpu/msm/adreno-gpulist.h

+1 −1
Original line number Diff line number Diff line
@@ -387,7 +387,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.patchid = 0,

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU |

			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC,

			ADRENO_IFPC | ADRENO_ACD,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a640_zap",

		.gpudev = &adreno_a6xx_gpudev,

drivers/gpu/msm/adreno.c

+4 −0
Original line number Diff line number Diff line
@@ -965,6 +965,10 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev, 
		if (of_property_read_u32(child, "qcom,bus-max",

			&level->bus_max))

			level->bus_max = level->bus_freq;



		if (of_property_read_u32(child, "qcom,dvm-val",

				&level->acd_dvm_val))

			level->acd_dvm_val = 0xFFFFFFFF;

	}



	return 0;

drivers/gpu/msm/adreno.h

+6 −0
Original line number Diff line number Diff line
@@ -123,6 +123,11 @@ 
#define ADRENO_MIN_VOLT BIT(15)

/* The core supports IO-coherent memory */

#define ADRENO_IOCOHERENT BIT(16)

/*

 * The GMU supports Adaptive Clock Distribution (ACD)

 * for droop mitigation

 */

#define ADRENO_ACD BIT(17)



/*

 * Adreno GPU quirks - control bits for various workarounds
@@ -233,6 +238,7 @@ enum adreno_gpurev { 
#define ADRENO_LM_CTRL      2

#define ADRENO_HWCG_CTRL    3

#define ADRENO_THROTTLING_CTRL 4

#define ADRENO_ACD_CTRL 5



/* VBIF,  GBIF halt request and ack mask */

#define GBIF_HALT_REQUEST       0x1E0