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Commit 89683fde authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown
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ASoC: tas2552: Correct PDM configuration register bit definitions 



The PDM clock can be selected via bit0-1.
PDM_DATA_ES bit is at bit2.

The code were trying to select BCLK as PDM reference clock but instead
it was selecting PLL and set the DATA_ES bit to 1.
Selecting the PLL output as reference clock as default does make sense,
but the driver should not change the PDM data edge.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1cf0f448

sound/soc/codecs/tas2552.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -376,7 +376,7 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec) 
				TAS2552_DIN_SRC_SEL_AVG_L_R | TAS2552_88_96KHZ);

				TAS2552_DIN_SRC_SEL_AVG_L_R | TAS2552_88_96KHZ);

	snd_soc_write(codec, TAS2552_DOUT, TAS2552_PDM_DATA_I);

	snd_soc_write(codec, TAS2552_DOUT, TAS2552_PDM_DATA_I);

	snd_soc_write(codec, TAS2552_OUTPUT_DATA, TAS2552_PDM_DATA_V_I | 0x8);

	snd_soc_write(codec, TAS2552_OUTPUT_DATA, TAS2552_PDM_DATA_V_I | 0x8);

	snd_soc_write(codec, TAS2552_PDM_CFG, TAS2552_PDM_BCLK_SEL);

	snd_soc_write(codec, TAS2552_PDM_CFG, TAS2552_PDM_CLK_SEL_PLL);

	snd_soc_write(codec, TAS2552_BOOST_PT_CTRL, TAS2552_APT_DELAY_200 |

	snd_soc_write(codec, TAS2552_BOOST_PT_CTRL, TAS2552_APT_DELAY_200 |

				TAS2552_APT_THRESH_2_1_7);

				TAS2552_APT_THRESH_2_1_7);

sound/soc/codecs/tas2552.h

+6 −6
Original line number Original line Diff line number Diff line
@@ -99,12 +99,12 @@ 
#define TAS2552_PDM_DATA_V_I	(0x11 << 6)

#define TAS2552_PDM_DATA_V_I	(0x11 << 6)





/* PDM CFG Register */

/* PDM CFG Register */

#define TAS2552_PDM_DATA_ES_RISE 0x4

#define TAS2552_PDM_CLK_SEL_PLL		(0x0 << 0)



#define TAS2552_PDM_CLK_SEL_IVCLKIN	(0x1 << 0)

#define TAS2552_PDM_PLL_CLK_SEL 0x00

#define TAS2552_PDM_CLK_SEL_BCLK	(0x2 << 0)

#define TAS2552_PDM_IV_CLK_SEL	(1 << 1)

#define TAS2552_PDM_CLK_SEL_MCLK	(0x3 << 0)

#define TAS2552_PDM_BCLK_SEL	(1 << 2)

#define TAS2552_PDM_CLK_SEL_MASK	TAS2552_PDM_CLK_SEL_MCLK

#define TAS2552_PDM_MCLK_SEL	(1 << 3)

#define TAS2552_PDM_DATA_ES	 	(1 << 2)





/* Boost pass-through register */

/* Boost pass-through register */

#define TAS2552_APT_DELAY_50	0x00

#define TAS2552_APT_DELAY_50	0x00