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Commit 8884d8c7 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Sebastian Hesselbarth
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arm64: dts: berlin4ct: add GPIO nodes 



Marvell berlin4ct SoC has 6 GPIO ports powered by snps,dw-apb-gpio. This
patch adds the corresponding device tree nodes.

Signed-off-by: default avatarJisheng Zhang <jszhang@marvell.com>
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
parent 6ff33f39

arch/arm64/boot/dts/marvell/berlin4ct.dtsi

+120 −0
Original line number Diff line number Diff line
@@ -135,6 +135,96 @@ 
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		};



		apb@e80000 {

			compatible = "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;



			ranges = <0 0xe80000 0x10000>;

			interrupt-parent = <&aic>;



			gpio0: gpio@0400 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0400 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porta: gpio-port@0 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <0>;

				};

			};



			gpio1: gpio@0800 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0800 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portb: gpio-port@1 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <1>;

				};

			};



			gpio2: gpio@0c00 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x0c00 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portc: gpio-port@2 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <2>;

				};

			};



			gpio3: gpio@1000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x1000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portd: gpio-port@3 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

					interrupt-controller;

					#interrupt-cells = <2>;

					interrupts = <3>;

				};

			};



			aic: interrupt-controller@3800 {

				compatible = "snps,dw-apb-ictl";

				reg = <0x3800 0x30>;

				interrupt-controller;

				#interrupt-cells = <1>;

				interrupt-parent = <&gic>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		apb@fc0000 {

			compatible = "simple-bus";

			#address-cells = <1>;
@@ -151,6 +241,36 @@ 
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			};



			sm_gpio0: gpio@8000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x8000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				porte: gpio-port@4 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

				};

			};



			sm_gpio1: gpio@9000 {

				compatible = "snps,dw-apb-gpio";

				reg = <0x9000 0x400>;

				#address-cells = <1>;

				#size-cells = <0>;



				portf: gpio-port@5 {

					compatible = "snps,dw-apb-gpio-port";

					gpio-controller;

					#gpio-cells = <2>;

					snps,nr-gpios = <32>;

					reg = <0>;

				};

			};



			uart0: uart@d000 {

				compatible = "snps,dw-apb-uart";

				reg = <0xd000 0x100>;