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Commit 885028e4 authored by Srinidhi Kasagar's avatar Srinidhi Kasagar Committed by Russell King
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ARM: 6741/1: errata: pl310 cache sync operation may be faulty 



The effect of cache sync operation is to drain the store buffer and
wait for all internal buffers to be empty. In normal conditions, store
buffer is able to merge the normal memory writes within its 32-byte
data buffers.  Due to this erratum present in r3p0, the effect of cache
sync operation on the store buffer still remains when the operation
completes. This means that the store buffer is always asked to drain
and this prevents it from merging any further writes.

This can severely affect performance on the write traffic esp. on
Normal memory NC one.

The proposed workaround is to replace the normal offset of cache sync
operation(0x730) by another offset targeting an unmapped PL310
register 0x740.

Signed-off-by: default avatarsrinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: default avatarLinus Walleij <linus.walleij@stericsson.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 0cc9d525

arch/arm/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -1177,6 +1177,21 @@ config ARM_ERRATA_743622 
	  visible impact on the overall performance or power consumption of the

	  processor.



config ARM_ERRATA_753970

	bool "ARM errata: cache sync operation may be faulty"

	depends on CACHE_PL310

	help

	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.



	  Under some condition the effect of cache sync operation on

	  the store buffer still remains when the operation completes.

	  This means that the store buffer is always asked to drain and

	  this prevents it from merging any further writes. The workaround

	  is to replace the normal offset of cache sync operation (0x730)

	  by another offset targeting an unmapped PL310 register 0x740.

	  This has the same effect as the cache sync operation: store buffer

	  drain and waiting for all buffers empty.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/include/asm/hardware/cache-l2x0.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#define L2X0_RAW_INTR_STAT		0x21C

#define L2X0_INTR_CLEAR			0x220

#define L2X0_CACHE_SYNC			0x730

#define L2X0_DUMMY_REG			0x740

#define L2X0_INV_LINE_PA		0x770

#define L2X0_INV_WAY			0x77C

#define L2X0_CLEAN_LINE_PA		0x7B0

arch/arm/mm/cache-l2x0.c

+6 −0
Original line number Diff line number Diff line
@@ -49,7 +49,13 @@ static inline void cache_wait(void __iomem *reg, unsigned long mask) 
static inline void cache_sync(void)

{

	void __iomem *base = l2x0_base;



#ifdef CONFIG_ARM_ERRATA_753970

	/* write to an unmmapped register */

	writel_relaxed(0, base + L2X0_DUMMY_REG);

#else

	writel_relaxed(0, base + L2X0_CACHE_SYNC);

#endif

	cache_wait(base + L2X0_CACHE_SYNC, 1);

}