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Commit 87d91db9 authored by Stanislaw Gruszka's avatar Stanislaw Gruszka Committed by John W. Linville
Browse files

rt2800: move RFCSR6_R2 & LDO_CFG0 setup to 3572 specific rfcsr init

parent 2971e66f
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+17 −17
Original line number Original line Diff line number Diff line
@@ -4709,6 +4709,9 @@ static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)


static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
{
{
	u8 rfcsr;
	u32 reg;

	rt2800_rf_init_calibration(rt2x00dev, 30);
	rt2800_rf_init_calibration(rt2x00dev, 30);


	rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
	rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
@@ -4742,6 +4745,20 @@ static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
	rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
	rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
	rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
	rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
	rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
	rt2800_rfcsr_write(rt2x00dev, 31, 0x10);

	rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
	rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);

	rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
	msleep(1);
	rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
}
}


static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
@@ -4994,23 +5011,6 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
		return 0;
		return 0;
	}
	}



	if (rt2x00_rt(rt2x00dev, RT3572)) {
		rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
		rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
		rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);

		rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
		msleep(1);
		rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
	}

	/*
	/*
	 * Set RX Filter calibration for 20MHz and 40MHz
	 * Set RX Filter calibration for 20MHz and 40MHz
	 */
	 */