Loading drivers/gpu/msm/adreno.h +12 −0 Original line number Diff line number Diff line Loading @@ -1360,6 +1360,18 @@ static inline int adreno_is_a640v2(struct adreno_device *adreno_dev) (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1); } static inline int adreno_is_a680v1(struct adreno_device *adreno_dev) { return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A680) && (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0); } static inline int adreno_is_a680v2(struct adreno_device *adreno_dev) { return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A680) && (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1); } /* * adreno_checkreg_off() - Checks the validity of a register enum * @adreno_dev: Pointer to adreno device Loading drivers/gpu/msm/adreno_a6xx_gmu.c +1 −1 Original line number Diff line number Diff line Loading @@ -86,7 +86,7 @@ static int _load_gmu_rpmh_ucode(struct kgsl_device *device) unsigned int cfg_offset, seq_offset; /* Offsets from the base PDC (if no PDC subsections in the DTSI) */ if (adreno_is_a640v2(adreno_dev)) { if ((adreno_is_a640v2(adreno_dev)) || (adreno_is_a680v2(adreno_dev))) { cfg_offset = 0x90000; seq_offset = 0x290000; } else { Loading Loading
drivers/gpu/msm/adreno.h +12 −0 Original line number Diff line number Diff line Loading @@ -1360,6 +1360,18 @@ static inline int adreno_is_a640v2(struct adreno_device *adreno_dev) (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1); } static inline int adreno_is_a680v1(struct adreno_device *adreno_dev) { return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A680) && (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0); } static inline int adreno_is_a680v2(struct adreno_device *adreno_dev) { return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A680) && (ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1); } /* * adreno_checkreg_off() - Checks the validity of a register enum * @adreno_dev: Pointer to adreno device Loading
drivers/gpu/msm/adreno_a6xx_gmu.c +1 −1 Original line number Diff line number Diff line Loading @@ -86,7 +86,7 @@ static int _load_gmu_rpmh_ucode(struct kgsl_device *device) unsigned int cfg_offset, seq_offset; /* Offsets from the base PDC (if no PDC subsections in the DTSI) */ if (adreno_is_a640v2(adreno_dev)) { if ((adreno_is_a640v2(adreno_dev)) || (adreno_is_a680v2(adreno_dev))) { cfg_offset = 0x90000; seq_offset = 0x290000; } else { Loading