Commit 878a84d5 authored Apr 20, 2015 by Andre Przywara Committed by Will Deacon Apr 27, 2015

arm64: add missing data types in smp_load_acquire/smp_store_release



Commit 8053871d ("smp: Fix smp_call_function_single_async()
locking") introduced a call to smp_load_acquire() with a u16 argument,
but we only cared about u32 and u64 types in that function so far.
This resulted in a compiler warning fortunately, pointing at an
uninitialized use. Due to the implementation structure the compiler
misses that bug in the smp_store_release(), though.
Add the u16 and u8 variants using ldarh/stlrh and ldarb/stlrb,
respectively. Together with the compiletime_assert_atomic_type() check
this should cover all cases now.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

parent b787f68c

arch/arm64/include/asm/barrier.h

+16 −0

Original line number	Diff line number	Diff line
		@@ -65,6 +65,14 @@ do { \
		do { \
		compiletime_assert_atomic_type(*p); \
		switch (sizeof(*p)) { \
		case 1: \
		asm volatile ("stlrb %w1, %0" \
		: "=Q" (*p) : "r" (v) : "memory"); \
		break; \
		case 2: \
		asm volatile ("stlrh %w1, %0" \
		: "=Q" (*p) : "r" (v) : "memory"); \
		break; \
		case 4: \
		asm volatile ("stlr %w1, %0" \
		: "=Q" (*p) : "r" (v) : "memory"); \
		@@ -81,6 +89,14 @@ do { \
		typeof(*p) ___p1; \
		compiletime_assert_atomic_type(*p); \
		switch (sizeof(*p)) { \
		case 1: \
		asm volatile ("ldarb %w0, %1" \
		: "=r" (___p1) : "Q" (*p) : "memory"); \
		break; \
		case 2: \
		asm volatile ("ldarh %w0, %1" \
		: "=r" (___p1) : "Q" (*p) : "memory"); \
		break; \
		case 4: \
		asm volatile ("ldar %w0, %1" \
		: "=r" (___p1) : "Q" (*p) : "memory"); \