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Commit 85eb968e authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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ARM: shmobile: r8a7740 legacy: Add missing INTCA clock for irqpin module 



This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state.
By making it available to the driver, we make sure it gets enabled when
needed, and allow it to be managed by system or runtime PM.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent a926a12b

arch/arm/mach-shmobile/clock-r8a7740.c

+6 −1
Original line number Diff line number Diff line
@@ -455,7 +455,7 @@ enum { 
	MSTP128, MSTP127, MSTP125,

	MSTP116, MSTP111, MSTP100, MSTP117,



	MSTP230,

	MSTP230, MSTP229,

	MSTP222,

	MSTP218, MSTP217, MSTP216, MSTP214,

	MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
@@ -479,6 +479,7 @@ static struct clk mstp_clks[MSTP_NR] = { 
	[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	SMSTPCR1,  0, 0), /* LCDC0 */



	[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR2, 30, 0), /* SCIFA6 */

	[MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR2, 29, 0), /* INTCA */

	[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR2, 22, 0), /* SCIFA7 */

	[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 18, 0), /* DMAC1 */

	[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 17, 0), /* DMAC2 */
@@ -575,6 +576,10 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_DEV_ID("sh-dma-engine.0",	&mstp_clks[MSTP218]),

	CLKDEV_DEV_ID("sh-sci.7",		&mstp_clks[MSTP222]),

	CLKDEV_DEV_ID("e6cd0000.serial",	&mstp_clks[MSTP222]),

	CLKDEV_DEV_ID("renesas_intc_irqpin.0",	&mstp_clks[MSTP229]),

	CLKDEV_DEV_ID("renesas_intc_irqpin.1",	&mstp_clks[MSTP229]),

	CLKDEV_DEV_ID("renesas_intc_irqpin.2",	&mstp_clks[MSTP229]),

	CLKDEV_DEV_ID("renesas_intc_irqpin.3",	&mstp_clks[MSTP229]),

	CLKDEV_DEV_ID("sh-sci.6",		&mstp_clks[MSTP230]),

	CLKDEV_DEV_ID("e6cc0000.serial",	&mstp_clks[MSTP230]),