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Commit 85b85c56 authored by Horia Geantă's avatar Horia Geantă Committed by Shawn Guo
Browse files

arm64: dts: ls1012a: add crypto node 



LS1012A has a SEC v5.4 security engine.

Signed-off-by: default avatarHoria Geantă <horia.geanta@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 893e2aad

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

+99 −1
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
 *     OTHER DEALINGS IN THE SOFTWARE.

 */



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/thermal/thermal.h>



/ {
@@ -51,6 +51,15 @@ 
	#address-cells = <2>;

	#size-cells = <2>;



	aliases {

		crypto = &crypto;

		rtic_a = &rtic_a;

		rtic_b = &rtic_b;

		rtic_c = &rtic_c;

		rtic_d = &rtic_d;

		sec_mon = &sec_mon;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -114,6 +123,95 @@ 
			big-endian;

		};



		crypto: crypto@1700000 {

			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",

				     "fsl,sec-v4.0";

			fsl,sec-era = <8>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x00 0x1700000 0x100000>;

			reg = <0x00 0x1700000 0x0 0x100000>;

			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;



			sec_jr0: jr@10000 {

				compatible = "fsl,sec-v5.4-job-ring",

					     "fsl,sec-v5.0-job-ring",

					     "fsl,sec-v4.0-job-ring";

				reg	   = <0x10000 0x10000>;

				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

			};



			sec_jr1: jr@20000 {

				compatible = "fsl,sec-v5.4-job-ring",

					     "fsl,sec-v5.0-job-ring",

					     "fsl,sec-v4.0-job-ring";

				reg	   = <0x20000 0x10000>;

				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

			};



			sec_jr2: jr@30000 {

				compatible = "fsl,sec-v5.4-job-ring",

					     "fsl,sec-v5.0-job-ring",

					     "fsl,sec-v4.0-job-ring";

				reg	   = <0x30000 0x10000>;

				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;

			};



			sec_jr3: jr@40000 {

				compatible = "fsl,sec-v5.4-job-ring",

					     "fsl,sec-v5.0-job-ring",

					     "fsl,sec-v4.0-job-ring";

				reg	   = <0x40000 0x10000>;

				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

			};



			rtic@60000 {

				compatible = "fsl,sec-v5.4-rtic",

					     "fsl,sec-v5.0-rtic",

					     "fsl,sec-v4.0-rtic";

				#address-cells = <1>;

				#size-cells = <1>;

				reg = <0x60000 0x100 0x60e00 0x18>;

				ranges = <0x0 0x60100 0x500>;



				rtic_a: rtic-a@0 {

					compatible = "fsl,sec-v5.4-rtic-memory",

						     "fsl,sec-v5.0-rtic-memory",

						     "fsl,sec-v4.0-rtic-memory";

					reg = <0x00 0x20 0x100 0x100>;

				};



				rtic_b: rtic-b@20 {

					compatible = "fsl,sec-v5.4-rtic-memory",

						     "fsl,sec-v5.0-rtic-memory",

						     "fsl,sec-v4.0-rtic-memory";

					reg = <0x20 0x20 0x200 0x100>;

				};



				rtic_c: rtic-c@40 {

					compatible = "fsl,sec-v5.4-rtic-memory",

						     "fsl,sec-v5.0-rtic-memory",

						     "fsl,sec-v4.0-rtic-memory";

					reg = <0x40 0x20 0x300 0x100>;

				};



				rtic_d: rtic-d@60 {

					compatible = "fsl,sec-v5.4-rtic-memory",

						     "fsl,sec-v5.0-rtic-memory",

						     "fsl,sec-v4.0-rtic-memory";

					reg = <0x60 0x20 0x400 0x100>;

				};

			};

		};



		sec_mon: sec_mon@1e90000 {

			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",

				     "fsl,sec-v4.0-mon";

			reg = <0x0 0x1e90000 0x0 0x10000>;

			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

		};



		dcfg: dcfg@1ee0000 {

			compatible = "fsl,ls1012a-dcfg",

				     "syscon";