drm/i915: s/ironlake_/intel_ for the enable_share_dpll function

}

/**

 * ironlake_enable_shared_dpll - enable PCH PLL

 * intel_enable_shared_dpll - enable PCH PLL

 * @dev_priv: i915 private structure

 * @pipe: pipe PLL to enable

 *

 * The PCH PLL needs to be enabled before the PCH transcoder, since it

 * drives the transcoder clock.

 */

static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)

static void intel_enable_shared_dpll(struct intel_crtc *crtc)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);

	/* PCH PLLs only available on ILK, SNB and IVB */

	BUG_ON(INTEL_INFO(dev)->gen < 5);

	if (WARN_ON(pll == NULL))

		return;

	 * Note that enable_shared_dpll tries to do the right thing, but

	 * get_shared_dpll unconditionally resets the pll - we need that to have

	 * the right LVDS enable sequence. */

	ironlake_enable_shared_dpll(intel_crtc);

	intel_enable_shared_dpll(intel_crtc);

	/* set transcoder timing, panel must allow it */

	assert_panel_unlocked(dev_priv, pipe);