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Commit 851050a5 authored by Mark Rutland's avatar Mark Rutland
Browse files

KVM: arm64: Use common sysreg definitions 



Now that we have common definitions for the remaining register encodings
required by KVM, make the KVM code use these, simplifying the
sys_reg_descs table and the genericv8_sys_regs table.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
parent 0d449541

arch/arm64/kvm/sys_regs.c

+24 −70
Original line number Diff line number Diff line
@@ -924,72 +924,36 @@ static const struct sys_reg_desc sys_reg_descs[] = { 


	{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },



	/* MPIDR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),

	  NULL, reset_mpidr, MPIDR_EL1 },

	/* SCTLR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),

	  access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },

	/* CPACR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),

	  NULL, reset_val, CPACR_EL1, 0 },

	/* TTBR0_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),

	  access_vm_reg, reset_unknown, TTBR0_EL1 },

	/* TTBR1_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),

	  access_vm_reg, reset_unknown, TTBR1_EL1 },

	/* TCR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),

	  access_vm_reg, reset_val, TCR_EL1, 0 },



	/* AFSR0_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),

	  access_vm_reg, reset_unknown, AFSR0_EL1 },

	/* AFSR1_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),

	  access_vm_reg, reset_unknown, AFSR1_EL1 },

	/* ESR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),

	  access_vm_reg, reset_unknown, ESR_EL1 },

	/* FAR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),

	  access_vm_reg, reset_unknown, FAR_EL1 },

	/* PAR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),

	  NULL, reset_unknown, PAR_EL1 },

	{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },

	{ SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },

	{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },

	{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },

	{ SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },

	{ SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },



	{ SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },

	{ SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },

	{ SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },

	{ SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },

	{ SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },



	{ SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },

	{ SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },



	/* MAIR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),

	  access_vm_reg, reset_unknown, MAIR_EL1 },

	/* AMAIR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),

	  access_vm_reg, reset_amair_el1, AMAIR_EL1 },

	{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },

	{ SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },



	/* VBAR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),

	  NULL, reset_val, VBAR_EL1, 0 },

	{ SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },



	{ SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },

	{ SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },



	/* CONTEXTIDR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),

	  access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },

	/* TPIDR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),

	  NULL, reset_unknown, TPIDR_EL1 },

	{ SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },

	{ SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },



	/* CNTKCTL_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),

	  NULL, reset_val, CNTKCTL_EL1, 0},

	{ SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},



	/* CSSELR_EL1 */

	{ Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),

	  NULL, reset_unknown, CSSELR_EL1 },

	{ SYS_DESC(SYS_CSSELR_EL1), NULL, reset_unknown, CSSELR_EL1 },



	{ SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, },

	{ SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
@@ -1009,12 +973,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	{ SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },

	{ SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },



	/* TPIDR_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),

	  NULL, reset_unknown, TPIDR_EL0 },

	/* TPIDRRO_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),

	  NULL, reset_unknown, TPIDRRO_EL0 },

	{ SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },

	{ SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },



	{ SYS_DESC(SYS_CNTP_TVAL_EL0), access_cntp_tval },

	{ SYS_DESC(SYS_CNTP_CTL_EL0), access_cntp_ctl },
@@ -1090,15 +1050,9 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	 */

	{ SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },



	/* DACR32_EL2 */

	{ Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),

	  NULL, reset_unknown, DACR32_EL2 },

	/* IFSR32_EL2 */

	{ Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),

	  NULL, reset_unknown, IFSR32_EL2 },

	/* FPEXC32_EL2 */

	{ Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),

	  NULL, reset_val, FPEXC32_EL2, 0x70 },

	{ SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },

	{ SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },

	{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x70 },

};



static bool trap_dbgidr(struct kvm_vcpu *vcpu,

arch/arm64/kvm/sys_regs_generic_v8.c

+1 −3
Original line number Diff line number Diff line
@@ -52,9 +52,7 @@ static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 
 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2

 */

static const struct sys_reg_desc genericv8_sys_regs[] = {

	/* ACTLR_EL1 */

	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),

	  access_actlr, reset_actlr, ACTLR_EL1 },

	{ SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },

};



static const struct sys_reg_desc genericv8_cp15_regs[] = {