Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 84f720ec authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes 

Daniel writes:

"Just a few smaller things:
- Fix up a pipe vs. plane confusion from a refactoring, fixes a regression
  from 3.1 (Anhua Xu).
- Fix ivb sprite pixel formats (Vijay).
- Fixup ppgtt pde placement for machines where the Bios artifically limits
  the availbale gtt space in the name of ... product differentiation
  (Chris). This fixes an oops.
- Yet another no_lvds quirk entry."

* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
  i915: Quirk no_lvds on Gigabyte GA-D525TUD ITX motherboard
  drm/i915: Use the correct size of the GTT for placing the per-process entries
  drm/i915: fix color order for BGR formats on IVB
  drm/i915: fix wrong order of parameters in port checking functions
parents f08859a9 a51d4ed0

drivers/gpu/drm/i915/i915_gem_gtt.c

+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) 
	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024

	 * entries. For aliasing ppgtt support we just steal them at the end for

	 * now. */

	first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES;

	first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;



	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);

	if (!ppgtt)

drivers/gpu/drm/i915/intel_display.c

+6 −6
Original line number Diff line number Diff line
@@ -1384,7 +1384,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 
				     enum pipe pipe, int reg)

{

	u32 val = I915_READ(reg);

	WARN(hdmi_pipe_enabled(dev_priv, val, pipe),

	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),

	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",

	     reg, pipe_name(pipe));
@@ -1404,13 +1404,13 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 


	reg = PCH_ADPA;

	val = I915_READ(reg);

	WARN(adpa_pipe_enabled(dev_priv, val, pipe),

	WARN(adpa_pipe_enabled(dev_priv, pipe, val),

	     "PCH VGA enabled on transcoder %c, should be disabled\n",

	     pipe_name(pipe));



	reg = PCH_LVDS;

	val = I915_READ(reg);

	WARN(lvds_pipe_enabled(dev_priv, val, pipe),

	WARN(lvds_pipe_enabled(dev_priv, pipe, val),

	     "PCH LVDS enabled on transcoder %c, should be disabled\n",

	     pipe_name(pipe));
@@ -1872,7 +1872,7 @@ static void disable_pch_hdmi(struct drm_i915_private *dev_priv, 
			     enum pipe pipe, int reg)

{

	u32 val = I915_READ(reg);

	if (hdmi_pipe_enabled(dev_priv, val, pipe)) {

	if (hdmi_pipe_enabled(dev_priv, pipe, val)) {

		DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",

			      reg, pipe);

		I915_WRITE(reg, val & ~PORT_ENABLE);
@@ -1894,12 +1894,12 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, 


	reg = PCH_ADPA;

	val = I915_READ(reg);

	if (adpa_pipe_enabled(dev_priv, val, pipe))

	if (adpa_pipe_enabled(dev_priv, pipe, val))

		I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);



	reg = PCH_LVDS;

	val = I915_READ(reg);

	if (lvds_pipe_enabled(dev_priv, val, pipe)) {

	if (lvds_pipe_enabled(dev_priv, pipe, val)) {

		DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);

		I915_WRITE(reg, val & ~LVDS_PORT_EN);

		POSTING_READ(reg);

drivers/gpu/drm/i915/intel_lvds.c

+8 −0
Original line number Diff line number Diff line
@@ -780,6 +780,14 @@ static const struct dmi_system_id intel_no_lvds[] = { 
			DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),

		},

	},

	{

		.callback = intel_no_lvds_dmi_callback,

		.ident = "Gigabyte GA-D525TUD",

		.matches = {

			DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),

			DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),

		},

	},



	{ }	/* terminating entry */

};

drivers/gpu/drm/i915/intel_sprite.c

+2 −2
Original line number Diff line number Diff line
@@ -60,11 +60,11 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 


	switch (fb->pixel_format) {

	case DRM_FORMAT_XBGR8888:

		sprctl |= SPRITE_FORMAT_RGBX888;

		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;

		pixel_size = 4;

		break;

	case DRM_FORMAT_XRGB8888:

		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;

		sprctl |= SPRITE_FORMAT_RGBX888;

		pixel_size = 4;

		break;

	case DRM_FORMAT_YUYV: