Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 849dcce3 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'amd-xgbe-updates' 



Tom Lendacky says:

====================
amd-xgbe: AMD XGBE driver updates 2016-11-10

This patch series is targeted at adding support for a new PCI version
of the hardware. As part of the new PCI device, there is a new PCS/PHY
interaction, ECC support, I2C sideband communication, SFP+ support and
more.

The following updates and fixes are included in this driver update series:

- Hardware workaround for possible incorrectly generated interrupts
  during software reset
- Hardware workaround for Tx timestamp register access order
- Add support for a PCI version of the device
- Increase the Rx queue limit to take advantage of the increased number
  of DMA channels that might be available
- Add support for a new DMA channel interrupt mode
- Add ECC support for the device memory
- Add support for using the integrated I2C controller for sideband
  communication
- Expose the phylib phy_aneg_done() function so it can be called by the
  driver
- Add support for SFP+ modules
- Add support for MDIO attached PHYs
- Add support for KR re-driver between the PCS/SerDes and an external
  PHY

This patch series is based on net-next.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f0a40400 d7445d1f

drivers/net/ethernet/aeroflex/greth.c

+0 −9
Original line number Original line Diff line number Diff line
@@ -1290,15 +1290,6 @@ static int greth_mdio_probe(struct net_device *dev) 
	return 0;

	return 0;

}

}





static inline int phy_aneg_done(struct phy_device *phydev)

{

	int retval;



	retval = phy_read(phydev, MII_BMSR);



	return (retval < 0) ? retval : (retval & BMSR_ANEGCOMPLETE);

}



static int greth_mdio_init(struct greth_private *greth)

static int greth_mdio_init(struct greth_private *greth)

{

{

	int ret;

	int ret;

drivers/net/ethernet/amd/Kconfig

+8 −2
Original line number Original line Diff line number Diff line
@@ -173,11 +173,13 @@ config SUNLANCE 




config AMD_XGBE

config AMD_XGBE

	tristate "AMD 10GbE Ethernet driver"

	tristate "AMD 10GbE Ethernet driver"

	depends on ((OF_NET && OF_ADDRESS) || ACPI) && HAS_IOMEM && HAS_DMA

	depends on ((OF_NET && OF_ADDRESS) || ACPI || PCI) && HAS_IOMEM && HAS_DMA

	depends on ARM64 || COMPILE_TEST

	depends on X86 || ARM64 || COMPILE_TEST

	select BITREVERSE

	select BITREVERSE

	select CRC32

	select CRC32

	select PTP_1588_CLOCK

	select PTP_1588_CLOCK

	select PHYLIB

	select AMD_XGBE_HAVE_ECC if X86

	---help---

	---help---

	  This driver supports the AMD 10GbE Ethernet device found on an

	  This driver supports the AMD 10GbE Ethernet device found on an

	  AMD SoC.

	  AMD SoC.
@@ -195,4 +197,8 @@ config AMD_XGBE_DCB 




	  If unsure, say N.

	  If unsure, say N.





config AMD_XGBE_HAVE_ECC

	bool

	default n



endif # NET_VENDOR_AMD
 
endif # NET_VENDOR_AMD

drivers/net/ethernet/amd/xgbe/Makefile

+2 −1
Original line number Original line Diff line number Diff line
@@ -3,8 +3,9 @@ obj-$(CONFIG_AMD_XGBE) += amd-xgbe.o 
amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \

amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \

		 xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \

		 xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \

		 xgbe-ptp.o \

		 xgbe-ptp.o \

		 xgbe-phy-v1.o \

		 xgbe-i2c.o xgbe-phy-v1.o xgbe-phy-v2.o \

		 xgbe-platform.o

		 xgbe-platform.o





amd-xgbe-$(CONFIG_PCI) += xgbe-pci.o

amd-xgbe-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o

amd-xgbe-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o

amd-xgbe-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o
 
amd-xgbe-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o

drivers/net/ethernet/amd/xgbe/xgbe-common.h

+314 −0
Original line number Original line Diff line number Diff line
@@ -159,6 +159,8 @@ 
#define DMA_ISR_MACIS_WIDTH		1

#define DMA_ISR_MACIS_WIDTH		1

#define DMA_ISR_MTLIS_INDEX		16

#define DMA_ISR_MTLIS_INDEX		16

#define DMA_ISR_MTLIS_WIDTH		1

#define DMA_ISR_MTLIS_WIDTH		1

#define DMA_MR_INTM_INDEX		12

#define DMA_MR_INTM_WIDTH		2

#define DMA_MR_SWR_INDEX		0

#define DMA_MR_SWR_INDEX		0

#define DMA_MR_SWR_WIDTH		1

#define DMA_MR_SWR_WIDTH		1

#define DMA_SBMR_EAME_INDEX		11

#define DMA_SBMR_EAME_INDEX		11
@@ -309,6 +311,11 @@ 
#define MAC_HWF0R			0x011c

#define MAC_HWF0R			0x011c

#define MAC_HWF1R			0x0120

#define MAC_HWF1R			0x0120

#define MAC_HWF2R			0x0124

#define MAC_HWF2R			0x0124

#define MAC_MDIOSCAR			0x0200

#define MAC_MDIOSCCDR			0x0204

#define MAC_MDIOISR			0x0214

#define MAC_MDIOIER			0x0218

#define MAC_MDIOCL22R			0x0220

#define MAC_GPIOCR			0x0278

#define MAC_GPIOCR			0x0278

#define MAC_GPIOSR			0x027c

#define MAC_GPIOSR			0x027c

#define MAC_MACA0HR			0x0300

#define MAC_MACA0HR			0x0300
@@ -409,10 +416,34 @@ 
#define MAC_ISR_MMCTXIS_WIDTH		1

#define MAC_ISR_MMCTXIS_WIDTH		1

#define MAC_ISR_PMTIS_INDEX		4

#define MAC_ISR_PMTIS_INDEX		4

#define MAC_ISR_PMTIS_WIDTH		1

#define MAC_ISR_PMTIS_WIDTH		1

#define MAC_ISR_SMI_INDEX		1

#define MAC_ISR_SMI_WIDTH		1

#define MAC_ISR_TSIS_INDEX		12

#define MAC_ISR_TSIS_INDEX		12

#define MAC_ISR_TSIS_WIDTH		1

#define MAC_ISR_TSIS_WIDTH		1

#define MAC_MACA1HR_AE_INDEX		31

#define MAC_MACA1HR_AE_INDEX		31

#define MAC_MACA1HR_AE_WIDTH		1

#define MAC_MACA1HR_AE_WIDTH		1

#define MAC_MDIOIER_SNGLCOMPIE_INDEX	12

#define MAC_MDIOIER_SNGLCOMPIE_WIDTH	1

#define MAC_MDIOISR_SNGLCOMPINT_INDEX	12

#define MAC_MDIOISR_SNGLCOMPINT_WIDTH	1

#define MAC_MDIOSCAR_DA_INDEX		21

#define MAC_MDIOSCAR_DA_WIDTH		5

#define MAC_MDIOSCAR_PA_INDEX		16

#define MAC_MDIOSCAR_PA_WIDTH		5

#define MAC_MDIOSCAR_RA_INDEX		0

#define MAC_MDIOSCAR_RA_WIDTH		16

#define MAC_MDIOSCAR_REG_INDEX		0

#define MAC_MDIOSCAR_REG_WIDTH		21

#define MAC_MDIOSCCDR_BUSY_INDEX	22

#define MAC_MDIOSCCDR_BUSY_WIDTH	1

#define MAC_MDIOSCCDR_CMD_INDEX		16

#define MAC_MDIOSCCDR_CMD_WIDTH		2

#define MAC_MDIOSCCDR_CR_INDEX		19

#define MAC_MDIOSCCDR_CR_WIDTH		3

#define MAC_MDIOSCCDR_DATA_INDEX	0

#define MAC_MDIOSCCDR_DATA_WIDTH	16

#define MAC_MDIOSCCDR_SADDR_INDEX	18

#define MAC_MDIOSCCDR_SADDR_WIDTH	1

#define MAC_PFR_HMC_INDEX		2

#define MAC_PFR_HMC_INDEX		2

#define MAC_PFR_HMC_WIDTH		1

#define MAC_PFR_HMC_WIDTH		1

#define MAC_PFR_HPF_INDEX		10

#define MAC_PFR_HPF_INDEX		10
@@ -858,8 +889,15 @@ 




/* PCS register offsets */

/* PCS register offsets */

#define PCS_V1_WINDOW_SELECT		0x03fc

#define PCS_V1_WINDOW_SELECT		0x03fc

#define PCS_V2_WINDOW_DEF		0x9060

#define PCS_V2_WINDOW_SELECT		0x9064

#define PCS_V2_WINDOW_SELECT		0x9064





/* PCS register entry bit positions and sizes */

#define PCS_V2_WINDOW_DEF_OFFSET_INDEX	6

#define PCS_V2_WINDOW_DEF_OFFSET_WIDTH	14

#define PCS_V2_WINDOW_DEF_SIZE_INDEX	2

#define PCS_V2_WINDOW_DEF_SIZE_WIDTH	4



/* SerDes integration register offsets */

/* SerDes integration register offsets */

#define SIR0_KR_RT_1			0x002c

#define SIR0_KR_RT_1			0x002c

#define SIR0_STATUS			0x0040

#define SIR0_STATUS			0x0040
@@ -902,6 +940,198 @@ 
#define RXTX_REG129_RXDFE_CONFIG_INDEX	14

#define RXTX_REG129_RXDFE_CONFIG_INDEX	14

#define RXTX_REG129_RXDFE_CONFIG_WIDTH	2

#define RXTX_REG129_RXDFE_CONFIG_WIDTH	2





/* MAC Control register offsets */

#define XP_PROP_0			0x0000

#define XP_PROP_1			0x0004

#define XP_PROP_2			0x0008

#define XP_PROP_3			0x000c

#define XP_PROP_4			0x0010

#define XP_PROP_5			0x0014

#define XP_MAC_ADDR_LO			0x0020

#define XP_MAC_ADDR_HI			0x0024

#define XP_ECC_ISR			0x0030

#define XP_ECC_IER			0x0034

#define XP_ECC_CNT0			0x003c

#define XP_ECC_CNT1			0x0040

#define XP_DRIVER_INT_REQ		0x0060

#define XP_DRIVER_INT_RO		0x0064

#define XP_DRIVER_SCRATCH_0		0x0068

#define XP_DRIVER_SCRATCH_1		0x006c

#define XP_INT_EN			0x0078

#define XP_I2C_MUTEX			0x0080

#define XP_MDIO_MUTEX			0x0084



/* MAC Control register entry bit positions and sizes */

#define XP_DRIVER_INT_REQ_REQUEST_INDEX		0

#define XP_DRIVER_INT_REQ_REQUEST_WIDTH		1

#define XP_DRIVER_INT_RO_STATUS_INDEX		0

#define XP_DRIVER_INT_RO_STATUS_WIDTH		1

#define XP_DRIVER_SCRATCH_0_COMMAND_INDEX	0

#define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH	8

#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX	8

#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH	8

#define XP_ECC_CNT0_RX_DED_INDEX		24

#define XP_ECC_CNT0_RX_DED_WIDTH		8

#define XP_ECC_CNT0_RX_SEC_INDEX		16

#define XP_ECC_CNT0_RX_SEC_WIDTH		8

#define XP_ECC_CNT0_TX_DED_INDEX		8

#define XP_ECC_CNT0_TX_DED_WIDTH		8

#define XP_ECC_CNT0_TX_SEC_INDEX		0

#define XP_ECC_CNT0_TX_SEC_WIDTH		8

#define XP_ECC_CNT1_DESC_DED_INDEX		8

#define XP_ECC_CNT1_DESC_DED_WIDTH		8

#define XP_ECC_CNT1_DESC_SEC_INDEX		0

#define XP_ECC_CNT1_DESC_SEC_WIDTH		8

#define XP_ECC_IER_DESC_DED_INDEX		0

#define XP_ECC_IER_DESC_DED_WIDTH		1

#define XP_ECC_IER_DESC_SEC_INDEX		1

#define XP_ECC_IER_DESC_SEC_WIDTH		1

#define XP_ECC_IER_RX_DED_INDEX			2

#define XP_ECC_IER_RX_DED_WIDTH			1

#define XP_ECC_IER_RX_SEC_INDEX			3

#define XP_ECC_IER_RX_SEC_WIDTH			1

#define XP_ECC_IER_TX_DED_INDEX			4

#define XP_ECC_IER_TX_DED_WIDTH			1

#define XP_ECC_IER_TX_SEC_INDEX			5

#define XP_ECC_IER_TX_SEC_WIDTH			1

#define XP_ECC_ISR_DESC_DED_INDEX		0

#define XP_ECC_ISR_DESC_DED_WIDTH		1

#define XP_ECC_ISR_DESC_SEC_INDEX		1

#define XP_ECC_ISR_DESC_SEC_WIDTH		1

#define XP_ECC_ISR_RX_DED_INDEX			2

#define XP_ECC_ISR_RX_DED_WIDTH			1

#define XP_ECC_ISR_RX_SEC_INDEX			3

#define XP_ECC_ISR_RX_SEC_WIDTH			1

#define XP_ECC_ISR_TX_DED_INDEX			4

#define XP_ECC_ISR_TX_DED_WIDTH			1

#define XP_ECC_ISR_TX_SEC_INDEX			5

#define XP_ECC_ISR_TX_SEC_WIDTH			1

#define XP_I2C_MUTEX_BUSY_INDEX			31

#define XP_I2C_MUTEX_BUSY_WIDTH			1

#define XP_I2C_MUTEX_ID_INDEX			29

#define XP_I2C_MUTEX_ID_WIDTH			2

#define XP_I2C_MUTEX_ACTIVE_INDEX		0

#define XP_I2C_MUTEX_ACTIVE_WIDTH		1

#define XP_MAC_ADDR_HI_VALID_INDEX		31

#define XP_MAC_ADDR_HI_VALID_WIDTH		1

#define XP_PROP_0_CONN_TYPE_INDEX		28

#define XP_PROP_0_CONN_TYPE_WIDTH		3

#define XP_PROP_0_MDIO_ADDR_INDEX		16

#define XP_PROP_0_MDIO_ADDR_WIDTH		5

#define XP_PROP_0_PORT_ID_INDEX			0

#define XP_PROP_0_PORT_ID_WIDTH			8

#define XP_PROP_0_PORT_MODE_INDEX		8

#define XP_PROP_0_PORT_MODE_WIDTH		4

#define XP_PROP_0_PORT_SPEEDS_INDEX		23

#define XP_PROP_0_PORT_SPEEDS_WIDTH		4

#define XP_PROP_1_MAX_RX_DMA_INDEX		24

#define XP_PROP_1_MAX_RX_DMA_WIDTH		5

#define XP_PROP_1_MAX_RX_QUEUES_INDEX		8

#define XP_PROP_1_MAX_RX_QUEUES_WIDTH		5

#define XP_PROP_1_MAX_TX_DMA_INDEX		16

#define XP_PROP_1_MAX_TX_DMA_WIDTH		5

#define XP_PROP_1_MAX_TX_QUEUES_INDEX		0

#define XP_PROP_1_MAX_TX_QUEUES_WIDTH		5

#define XP_PROP_2_RX_FIFO_SIZE_INDEX		16

#define XP_PROP_2_RX_FIFO_SIZE_WIDTH		16

#define XP_PROP_2_TX_FIFO_SIZE_INDEX		0

#define XP_PROP_2_TX_FIFO_SIZE_WIDTH		16

#define XP_PROP_3_GPIO_MASK_INDEX		28

#define XP_PROP_3_GPIO_MASK_WIDTH		4

#define XP_PROP_3_GPIO_MOD_ABS_INDEX		20

#define XP_PROP_3_GPIO_MOD_ABS_WIDTH		4

#define XP_PROP_3_GPIO_RATE_SELECT_INDEX	16

#define XP_PROP_3_GPIO_RATE_SELECT_WIDTH	4

#define XP_PROP_3_GPIO_RX_LOS_INDEX		24

#define XP_PROP_3_GPIO_RX_LOS_WIDTH		4

#define XP_PROP_3_GPIO_TX_FAULT_INDEX		12

#define XP_PROP_3_GPIO_TX_FAULT_WIDTH		4

#define XP_PROP_3_GPIO_ADDR_INDEX		8

#define XP_PROP_3_GPIO_ADDR_WIDTH		3

#define XP_PROP_3_MDIO_RESET_INDEX		0

#define XP_PROP_3_MDIO_RESET_WIDTH		2

#define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX	8

#define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH	3

#define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX	12

#define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH	4

#define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX	4

#define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH	2

#define XP_PROP_4_MUX_ADDR_HI_INDEX		8

#define XP_PROP_4_MUX_ADDR_HI_WIDTH		5

#define XP_PROP_4_MUX_ADDR_LO_INDEX		0

#define XP_PROP_4_MUX_ADDR_LO_WIDTH		3

#define XP_PROP_4_MUX_CHAN_INDEX		4

#define XP_PROP_4_MUX_CHAN_WIDTH		3

#define XP_PROP_4_REDRV_ADDR_INDEX		16

#define XP_PROP_4_REDRV_ADDR_WIDTH		7

#define XP_PROP_4_REDRV_IF_INDEX		23

#define XP_PROP_4_REDRV_IF_WIDTH		1

#define XP_PROP_4_REDRV_LANE_INDEX		24

#define XP_PROP_4_REDRV_LANE_WIDTH		3

#define XP_PROP_4_REDRV_MODEL_INDEX		28

#define XP_PROP_4_REDRV_MODEL_WIDTH		3

#define XP_PROP_4_REDRV_PRESENT_INDEX		31

#define XP_PROP_4_REDRV_PRESENT_WIDTH		1



/* I2C Control register offsets */

#define IC_CON					0x0000

#define IC_TAR					0x0004

#define IC_DATA_CMD				0x0010

#define IC_INTR_STAT				0x002c

#define IC_INTR_MASK				0x0030

#define IC_RAW_INTR_STAT			0x0034

#define IC_CLR_INTR				0x0040

#define IC_CLR_TX_ABRT				0x0054

#define IC_CLR_STOP_DET				0x0060

#define IC_ENABLE				0x006c

#define IC_TXFLR				0x0074

#define IC_RXFLR				0x0078

#define IC_TX_ABRT_SOURCE			0x0080

#define IC_ENABLE_STATUS			0x009c

#define IC_COMP_PARAM_1				0x00f4



/* I2C Control register entry bit positions and sizes */

#define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX	2

#define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH	2

#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX	8

#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH	8

#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX	16

#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH	8

#define IC_CON_MASTER_MODE_INDEX		0

#define IC_CON_MASTER_MODE_WIDTH		1

#define IC_CON_RESTART_EN_INDEX			5

#define IC_CON_RESTART_EN_WIDTH			1

#define IC_CON_RX_FIFO_FULL_HOLD_INDEX		9

#define IC_CON_RX_FIFO_FULL_HOLD_WIDTH		1

#define IC_CON_SLAVE_DISABLE_INDEX		6

#define IC_CON_SLAVE_DISABLE_WIDTH		1

#define IC_CON_SPEED_INDEX			1

#define IC_CON_SPEED_WIDTH			2

#define IC_DATA_CMD_CMD_INDEX			8

#define IC_DATA_CMD_CMD_WIDTH			1

#define IC_DATA_CMD_STOP_INDEX			9

#define IC_DATA_CMD_STOP_WIDTH			1

#define IC_ENABLE_ABORT_INDEX			1

#define IC_ENABLE_ABORT_WIDTH			1

#define IC_ENABLE_EN_INDEX			0

#define IC_ENABLE_EN_WIDTH			1

#define IC_ENABLE_STATUS_EN_INDEX		0

#define IC_ENABLE_STATUS_EN_WIDTH		1

#define IC_INTR_MASK_TX_EMPTY_INDEX		4

#define IC_INTR_MASK_TX_EMPTY_WIDTH		1

#define IC_RAW_INTR_STAT_RX_FULL_INDEX		2

#define IC_RAW_INTR_STAT_RX_FULL_WIDTH		1

#define IC_RAW_INTR_STAT_STOP_DET_INDEX		9

#define IC_RAW_INTR_STAT_STOP_DET_WIDTH		1

#define IC_RAW_INTR_STAT_TX_ABRT_INDEX		6

#define IC_RAW_INTR_STAT_TX_ABRT_WIDTH		1

#define IC_RAW_INTR_STAT_TX_EMPTY_INDEX		4

#define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH		1



/* I2C Control register value */

#define IC_TX_ABRT_7B_ADDR_NOACK		0x0001

#define IC_TX_ABRT_ARB_LOST			0x1000



/* Descriptor/Packet entry bit positions and sizes */

/* Descriptor/Packet entry bit positions and sizes */

#define RX_PACKET_ERRORS_CRC_INDEX		2

#define RX_PACKET_ERRORS_CRC_INDEX		2

#define RX_PACKET_ERRORS_CRC_WIDTH		1

#define RX_PACKET_ERRORS_CRC_WIDTH		1
@@ -1078,6 +1308,14 @@ 
#define MDIO_VEND2_CTRL1_AN_RESTART	BIT(9)

#define MDIO_VEND2_CTRL1_AN_RESTART	BIT(9)

#endif

#endif





#ifndef MDIO_VEND2_CTRL1_SS6

#define MDIO_VEND2_CTRL1_SS6		BIT(6)

#endif



#ifndef MDIO_VEND2_CTRL1_SS13

#define MDIO_VEND2_CTRL1_SS13		BIT(13)

#endif



/* MDIO mask values */

/* MDIO mask values */

#define XGBE_AN_CL73_INT_CMPLT		BIT(0)

#define XGBE_AN_CL73_INT_CMPLT		BIT(0)

#define XGBE_AN_CL73_INC_LINK		BIT(1)

#define XGBE_AN_CL73_INC_LINK		BIT(1)
@@ -1240,6 +1478,16 @@ do { \ 
/* Macros for building, reading or writing register values or bits

/* Macros for building, reading or writing register values or bits

 * within the register values of XPCS registers.

 * within the register values of XPCS registers.

 */

 */

#define XPCS_GET_BITS(_var, _prefix, _field)				\

	GET_BITS((_var),                                                \

		 _prefix##_##_field##_INDEX,                            \

		 _prefix##_##_field##_WIDTH)



#define XPCS_SET_BITS(_var, _prefix, _field, _val)                      \

	SET_BITS((_var),                                                \

		 _prefix##_##_field##_INDEX,                            \

		 _prefix##_##_field##_WIDTH, (_val))



#define XPCS32_IOWRITE(_pdata, _off, _val)				\

#define XPCS32_IOWRITE(_pdata, _off, _val)				\

	iowrite32(_val, (_pdata)->xpcs_regs + (_off))

	iowrite32(_val, (_pdata)->xpcs_regs + (_off))
@@ -1328,6 +1576,72 @@ do { \ 
	XRXTX_IOWRITE((_pdata), _reg, reg_val);				\

	XRXTX_IOWRITE((_pdata), _reg, reg_val);				\

} while (0)

} while (0)





/* Macros for building, reading or writing register values or bits

 * within the register values of MAC Control registers.

 */

#define XP_GET_BITS(_var, _prefix, _field)				\

	GET_BITS((_var),						\

		 _prefix##_##_field##_INDEX,				\

		 _prefix##_##_field##_WIDTH)



#define XP_SET_BITS(_var, _prefix, _field, _val)			\

	SET_BITS((_var),						\

		 _prefix##_##_field##_INDEX,				\

		 _prefix##_##_field##_WIDTH, (_val))



#define XP_IOREAD(_pdata, _reg)						\

	ioread32((_pdata)->xprop_regs + (_reg))



#define XP_IOREAD_BITS(_pdata, _reg, _field)				\

	GET_BITS(XP_IOREAD((_pdata), (_reg)),				\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH)



#define XP_IOWRITE(_pdata, _reg, _val)					\

	iowrite32((_val), (_pdata)->xprop_regs + (_reg))



#define XP_IOWRITE_BITS(_pdata, _reg, _field, _val)			\

do {									\

	u32 reg_val = XP_IOREAD((_pdata), (_reg));			\

	SET_BITS(reg_val,						\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH, (_val));			\

	XP_IOWRITE((_pdata), (_reg), reg_val);				\

} while (0)



/* Macros for building, reading or writing register values or bits

 * within the register values of I2C Control registers.

 */

#define XI2C_GET_BITS(_var, _prefix, _field)				\

	GET_BITS((_var),						\

		 _prefix##_##_field##_INDEX,				\

		 _prefix##_##_field##_WIDTH)



#define XI2C_SET_BITS(_var, _prefix, _field, _val)			\

	SET_BITS((_var),						\

		 _prefix##_##_field##_INDEX,				\

		 _prefix##_##_field##_WIDTH, (_val))



#define XI2C_IOREAD(_pdata, _reg)					\

	ioread32((_pdata)->xi2c_regs + (_reg))



#define XI2C_IOREAD_BITS(_pdata, _reg, _field)				\

	GET_BITS(XI2C_IOREAD((_pdata), (_reg)),				\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH)



#define XI2C_IOWRITE(_pdata, _reg, _val)				\

	iowrite32((_val), (_pdata)->xi2c_regs + (_reg))



#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val)			\

do {									\

	u32 reg_val = XI2C_IOREAD((_pdata), (_reg));			\

	SET_BITS(reg_val,						\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH, (_val));			\

	XI2C_IOWRITE((_pdata), (_reg), reg_val);			\

} while (0)



/* Macros for building, reading or writing register values or bits

/* Macros for building, reading or writing register values or bits

 * using MDIO.  Different from above because of the use of standardized

 * using MDIO.  Different from above because of the use of standardized

 * Linux include values.  No shifting is performed with the bit

 * Linux include values.  No shifting is performed with the bit

drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c

+152 −0
Original line number Original line Diff line number Diff line
@@ -316,6 +316,126 @@ static const struct file_operations xpcs_reg_value_fops = { 
	.write = xpcs_reg_value_write,

	.write = xpcs_reg_value_write,

};

};





static ssize_t xprop_reg_addr_read(struct file *filp, char __user *buffer,

				   size_t count, loff_t *ppos)

{

	struct xgbe_prv_data *pdata = filp->private_data;



	return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xprop_reg);

}



static ssize_t xprop_reg_addr_write(struct file *filp,

				    const char __user *buffer,

				    size_t count, loff_t *ppos)

{

	struct xgbe_prv_data *pdata = filp->private_data;



	return xgbe_common_write(buffer, count, ppos,

				 &pdata->debugfs_xprop_reg);

}



static ssize_t xprop_reg_value_read(struct file *filp, char __user *buffer,

				    size_t count, loff_t *ppos)

{

	struct xgbe_prv_data *pdata = filp->private_data;

	unsigned int value;



	value = XP_IOREAD(pdata, pdata->debugfs_xprop_reg);



	return xgbe_common_read(buffer, count, ppos, value);

}



static ssize_t xprop_reg_value_write(struct file *filp,

				     const char __user *buffer,

				     size_t count, loff_t *ppos)

{

	struct xgbe_prv_data *pdata = filp->private_data;

	unsigned int value;

	ssize_t len;



	len = xgbe_common_write(buffer, count, ppos, &value);

	if (len < 0)

		return len;



	XP_IOWRITE(pdata, pdata->debugfs_xprop_reg, value);



	return len;

}



static const struct file_operations xprop_reg_addr_fops = {

	.owner = THIS_MODULE,

	.open = simple_open,

	.read =  xprop_reg_addr_read,

	.write = xprop_reg_addr_write,

};



static const struct file_operations xprop_reg_value_fops = {

	.owner = THIS_MODULE,

	.open = simple_open,

	.read =  xprop_reg_value_read,

	.write = xprop_reg_value_write,

};



static ssize_t xi2c_reg_addr_read(struct file *filp, char __user *buffer,

				  size_t count, loff_t *ppos)

{

	struct xgbe_prv_data *pdata = filp->private_data;



	return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xi2c_reg);

}



static ssize_t xi2c_reg_addr_write(struct file *filp,

				   const char __user *buffer,

				   size_t count, loff_t *ppos)

{

	struct xgbe_prv_data *pdata = filp->private_data;



	return xgbe_common_write(buffer, count, ppos,

				 &pdata->debugfs_xi2c_reg);

}



static ssize_t xi2c_reg_value_read(struct file *filp, char __user *buffer,

				   size_t count, loff_t *ppos)

{

	struct xgbe_prv_data *pdata = filp->private_data;

	unsigned int value;



	value = XI2C_IOREAD(pdata, pdata->debugfs_xi2c_reg);



	return xgbe_common_read(buffer, count, ppos, value);

}



static ssize_t xi2c_reg_value_write(struct file *filp,

				    const char __user *buffer,

				    size_t count, loff_t *ppos)

{

	struct xgbe_prv_data *pdata = filp->private_data;

	unsigned int value;

	ssize_t len;



	len = xgbe_common_write(buffer, count, ppos, &value);

	if (len < 0)

		return len;



	XI2C_IOWRITE(pdata, pdata->debugfs_xi2c_reg, value);



	return len;

}



static const struct file_operations xi2c_reg_addr_fops = {

	.owner = THIS_MODULE,

	.open = simple_open,

	.read =  xi2c_reg_addr_read,

	.write = xi2c_reg_addr_write,

};



static const struct file_operations xi2c_reg_value_fops = {

	.owner = THIS_MODULE,

	.open = simple_open,

	.read =  xi2c_reg_value_read,

	.write = xi2c_reg_value_write,

};



void xgbe_debugfs_init(struct xgbe_prv_data *pdata)

void xgbe_debugfs_init(struct xgbe_prv_data *pdata)

{

{

	struct dentry *pfile;

	struct dentry *pfile;
@@ -367,6 +487,38 @@ void xgbe_debugfs_init(struct xgbe_prv_data *pdata) 
	if (!pfile)

	if (!pfile)

		netdev_err(pdata->netdev, "debugfs_create_file failed\n");

		netdev_err(pdata->netdev, "debugfs_create_file failed\n");





	if (pdata->xprop_regs) {

		pfile = debugfs_create_file("xprop_register", 0600,

					    pdata->xgbe_debugfs, pdata,

					    &xprop_reg_addr_fops);

		if (!pfile)

			netdev_err(pdata->netdev,

				   "debugfs_create_file failed\n");



		pfile = debugfs_create_file("xprop_register_value", 0600,

					    pdata->xgbe_debugfs, pdata,

					    &xprop_reg_value_fops);

		if (!pfile)

			netdev_err(pdata->netdev,

				   "debugfs_create_file failed\n");

	}



	if (pdata->xi2c_regs) {

		pfile = debugfs_create_file("xi2c_register", 0600,

					    pdata->xgbe_debugfs, pdata,

					    &xi2c_reg_addr_fops);

		if (!pfile)

			netdev_err(pdata->netdev,

				   "debugfs_create_file failed\n");



		pfile = debugfs_create_file("xi2c_register_value", 0600,

					    pdata->xgbe_debugfs, pdata,

					    &xi2c_reg_value_fops);

		if (!pfile)

			netdev_err(pdata->netdev,

				   "debugfs_create_file failed\n");

	}



	kfree(buf);

	kfree(buf);

}

}