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Commit 82da361c authored by Zhiqiang Tu's avatar Zhiqiang Tu Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add interrupt for 4-wire uart on sa8155 vm. 



4-wire uart data transfer requires QUPv3 SE irq.

Change-Id: I6e1aec8ea368c32366de8ac1d7ac757cbf3a9c0b
Signed-off-by: default avatarZhiqiang Tu <ztu@codeaurora.org>
parent c1b1f71e
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