Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 82a19551 authored by Jonathan Corbet's avatar Jonathan Corbet
Browse files

Docs: fix table problems in ras.rst 



Two table problems caused the PDF build to fail:

 - Evidently multirow cells are not appreciated in table headers,
   so remove such from the "CS Rows" table.

 - The logging message structure table was incorrectly formatted,
   with two "+" instead of "|".  The HTML build is forgiving of such
   things, but PDF is not.

Acked-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
Signed-off-by: default avatarJonathan Corbet <corbet@lwn.net>
parent 633d612b

Documentation/admin-guide/ras.rst

+5 −5
Original line number Diff line number Diff line
@@ -344,9 +344,9 @@ for more than 2 channels, like Fully Buffered DIMMs (FB-DIMMs) memory 
controllers. The following example will assume 2 channels:



	+------------+-----------------------+

	| Chip       |       Channels        |

	| Select     +-----------+-----------+

	| rows       |  ``ch0``  |  ``ch1``  |

	| CS Rows    |       Channels        |

	+------------+-----------+-----------+

	|            |  ``ch0``  |  ``ch1``  |

	+============+===========+===========+

	| ``csrow0`` |  DIMM_A0  |  DIMM_B0  |

	+------------+           |           |
@@ -698,7 +698,7 @@ information indicating that errors have been detected:: 
The structure of the message is:



	+---------------------------------------+-------------+

	| Content                               + Example     |

	| Content                               | Example     |

	+=======================================+=============+

	| The memory controller                 | MC0         |

	+---------------------------------------+-------------+
@@ -713,7 +713,7 @@ The structure of the message is: 
	+---------------------------------------+-------------+

	| The error syndrome                    | 0xb741      |

	+---------------------------------------+-------------+

	| Memory row                            | row 0       +

	| Memory row                            | row 0       |

	+---------------------------------------+-------------+

	| Memory channel                        | channel 1   |

	+---------------------------------------+-------------+