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Commit 822974ae authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: enable DIP before enabling each InfoFrame 



So the write_infoframe function can assume the DIP is on.

V2: Be more defensive and add WARN().

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f278d972

drivers/gpu/drm/i915/intel_hdmi.c

+22 −8
Original line number Diff line number Diff line
@@ -124,11 +124,12 @@ static void g4x_write_infoframe(struct drm_encoder *encoder, 
	u32 val = I915_READ(VIDEO_DIP_CTL);

	unsigned i, len = DIP_HEADER_SIZE + frame->len;



	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");



	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */

	val |= g4x_infoframe_index(frame);



	val &= ~g4x_infoframe_enable(frame);

	val |= VIDEO_DIP_ENABLE;



	I915_WRITE(VIDEO_DIP_CTL, val);
@@ -155,13 +156,14 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, 
	unsigned i, len = DIP_HEADER_SIZE + frame->len;

	u32 val = I915_READ(reg);



	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");



	intel_wait_for_vblank(dev, intel_crtc->pipe);



	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */

	val |= g4x_infoframe_index(frame);



	val &= ~g4x_infoframe_enable(frame);

	val |= VIDEO_DIP_ENABLE;



	I915_WRITE(reg, val);
@@ -188,6 +190,8 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, 
	unsigned i, len = DIP_HEADER_SIZE + frame->len;

	u32 val = I915_READ(reg);



	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");



	intel_wait_for_vblank(dev, intel_crtc->pipe);



	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
@@ -195,13 +199,9 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, 


	/* The DIP control register spec says that we need to update the AVI

	 * infoframe without clearing its enable bit */

	if (frame->type == DIP_TYPE_AVI)

		val |= VIDEO_DIP_ENABLE_AVI;

	else

	if (frame->type != DIP_TYPE_AVI)

		val &= ~g4x_infoframe_enable(frame);



	val |= VIDEO_DIP_ENABLE;



	I915_WRITE(reg, val);



	for (i = 0; i < len; i += 4) {
@@ -227,13 +227,14 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, 
	unsigned i, len = DIP_HEADER_SIZE + frame->len;

	u32 val = I915_READ(reg);



	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");



	intel_wait_for_vblank(dev, intel_crtc->pipe);



	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */

	val |= g4x_infoframe_index(frame);



	val &= ~g4x_infoframe_enable(frame);

	val |= VIDEO_DIP_ENABLE;



	I915_WRITE(reg, val);
@@ -356,6 +357,8 @@ static void g4x_set_infoframes(struct drm_encoder *encoder, 
		return;

	}



	val |= VIDEO_DIP_ENABLE;



	I915_WRITE(reg, val);



	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
@@ -397,6 +400,8 @@ static void ibx_set_infoframes(struct drm_encoder *encoder, 
		return;

	}



	val |= VIDEO_DIP_ENABLE;



	I915_WRITE(reg, val);



	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
@@ -423,6 +428,11 @@ static void cpt_set_infoframes(struct drm_encoder *encoder, 
		return;

	}



	/* Set both together, unset both together: see the spec. */

	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;



	I915_WRITE(reg, val);



	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);

	intel_hdmi_set_spd_infoframe(encoder);

}
@@ -447,6 +457,10 @@ static void vlv_set_infoframes(struct drm_encoder *encoder, 
		return;

	}



	val |= VIDEO_DIP_ENABLE;



	I915_WRITE(reg, val);



	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);

	intel_hdmi_set_spd_infoframe(encoder);

}