Loading drivers/gpu/msm/adreno_a6xx_gmu.c +3 −3 Original line number Diff line number Diff line Loading @@ -902,11 +902,11 @@ static int a6xx_gmu_wait_for_lowest_idle(struct adreno_device *adreno_dev) /* Collect abort data to help with debugging */ gmu_core_regread(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, ®2); gmu_core_regread(device, A6XX_CP_STATUS_1, ®3); kgsl_regread(device, A6XX_CP_STATUS_1, ®3); gmu_core_regread(device, A6XX_GMU_RBBM_INT_UNMASKED_STATUS, ®4); gmu_core_regread(device, A6XX_GMU_GMU_PWR_COL_KEEPALIVE, ®5); gmu_core_regread(device, A6XX_CP_CP2GMU_STATUS, ®6); gmu_core_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, ®7); kgsl_regread(device, A6XX_CP_CP2GMU_STATUS, ®6); kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, ®7); gmu_core_regread(device, A6XX_GMU_AO_SPARE_CNTL, ®8); dev_err(&gmu->pdev->dev, Loading drivers/gpu/msm/adreno_a6xx_rgmu.c +3 −3 Original line number Diff line number Diff line Loading @@ -313,11 +313,11 @@ static int a6xx_rgmu_wait_for_lowest_idle(struct adreno_device *adreno_dev) gmu_core_regread(device, A6XX_RGMU_CX_PCC_DEBUG, ®[1]); gmu_core_regread(device, A6XX_RGMU_CX_PCC_STATUS, ®[2]); gmu_core_regread(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, ®[3]); gmu_core_regread(device, A6XX_CP_STATUS_1, ®[4]); kgsl_regread(device, A6XX_CP_STATUS_1, ®[4]); gmu_core_regread(device, A6XX_GMU_RBBM_INT_UNMASKED_STATUS, ®[5]); gmu_core_regread(device, A6XX_GMU_GMU_PWR_COL_KEEPALIVE, ®[6]); gmu_core_regread(device, A6XX_CP_CP2GMU_STATUS, ®[7]); gmu_core_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, ®[8]); kgsl_regread(device, A6XX_CP_CP2GMU_STATUS, ®[7]); kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, ®[8]); gmu_core_regread(device, A6XX_GMU_AO_SPARE_CNTL, ®[9]); dev_err(&rgmu->pdev->dev, Loading Loading
drivers/gpu/msm/adreno_a6xx_gmu.c +3 −3 Original line number Diff line number Diff line Loading @@ -902,11 +902,11 @@ static int a6xx_gmu_wait_for_lowest_idle(struct adreno_device *adreno_dev) /* Collect abort data to help with debugging */ gmu_core_regread(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, ®2); gmu_core_regread(device, A6XX_CP_STATUS_1, ®3); kgsl_regread(device, A6XX_CP_STATUS_1, ®3); gmu_core_regread(device, A6XX_GMU_RBBM_INT_UNMASKED_STATUS, ®4); gmu_core_regread(device, A6XX_GMU_GMU_PWR_COL_KEEPALIVE, ®5); gmu_core_regread(device, A6XX_CP_CP2GMU_STATUS, ®6); gmu_core_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, ®7); kgsl_regread(device, A6XX_CP_CP2GMU_STATUS, ®6); kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, ®7); gmu_core_regread(device, A6XX_GMU_AO_SPARE_CNTL, ®8); dev_err(&gmu->pdev->dev, Loading
drivers/gpu/msm/adreno_a6xx_rgmu.c +3 −3 Original line number Diff line number Diff line Loading @@ -313,11 +313,11 @@ static int a6xx_rgmu_wait_for_lowest_idle(struct adreno_device *adreno_dev) gmu_core_regread(device, A6XX_RGMU_CX_PCC_DEBUG, ®[1]); gmu_core_regread(device, A6XX_RGMU_CX_PCC_STATUS, ®[2]); gmu_core_regread(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, ®[3]); gmu_core_regread(device, A6XX_CP_STATUS_1, ®[4]); kgsl_regread(device, A6XX_CP_STATUS_1, ®[4]); gmu_core_regread(device, A6XX_GMU_RBBM_INT_UNMASKED_STATUS, ®[5]); gmu_core_regread(device, A6XX_GMU_GMU_PWR_COL_KEEPALIVE, ®[6]); gmu_core_regread(device, A6XX_CP_CP2GMU_STATUS, ®[7]); gmu_core_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, ®[8]); kgsl_regread(device, A6XX_CP_CP2GMU_STATUS, ®[7]); kgsl_regread(device, A6XX_CP_CONTEXT_SWITCH_CNTL, ®[8]); gmu_core_regread(device, A6XX_GMU_AO_SPARE_CNTL, ®[9]); dev_err(&rgmu->pdev->dev, Loading