Merge "ARM: config: Enable different CONFIG_MMC flags for sdm640" (81b1a2df) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sdm640-pinctrl.dtsi

+112 −0

Original line number	Diff line number	Diff line
		@@ -47,5 +47,117 @@
		};
		};
		};

		/* SDC pin type */
		sdc1_clk_on: sdc1_clk_on {
		config {
		pins = "sdc1_clk";
		bias-disable; /* NO pull */
		drive-strength = <16>; /* 16 MA */
		};
		};

		sdc1_clk_off: sdc1_clk_off {
		config {
		pins = "sdc1_clk";
		bias-disable; /* NO pull */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc1_cmd_on: sdc1_cmd_on {
		config {
		pins = "sdc1_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc1_cmd_off: sdc1_cmd_off {
		config {
		pins = "sdc1_cmd";
		num-grp-pins = <1>;
		bias-pull-up; /* pull up */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc1_data_on: sdc1_data_on {
		config {
		pins = "sdc1_data";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc1_data_off: sdc1_data_off {
		config {
		pins = "sdc1_data";
		bias-pull-up; /* pull up */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc1_rclk_on: sdc1_rclk_on {
		config {
		pins = "sdc1_rclk";
		bias-pull-down; /* pull down */
		};
		};

		sdc1_rclk_off: sdc1_rclk_off {
		config {
		pins = "sdc1_rclk";
		bias-pull-down; /* pull down */
		};
		};

		sdc2_clk_on: sdc2_clk_on {
		config {
		pins = "sdc2_clk";
		bias-disable; /* NO pull */
		drive-strength = <16>; /* 16 MA */
		};
		};

		sdc2_clk_off: sdc2_clk_off {
		config {
		pins = "sdc2_clk";
		bias-disable; /* NO pull */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc2_cmd_on: sdc2_cmd_on {
		config {
		pins = "sdc2_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_cmd_off: sdc2_cmd_off {
		config {
		pins = "sdc2_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <2>; /* 2 MA */
		};
		};

		sdc2_data_on: sdc2_data_on {
		config {
		pins = "sdc2_data";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_data_off: sdc2_data_off {
		config {
		pins = "sdc2_data";
		bias-pull-up; /* pull up */
		drive-strength = <2>; /* 2 MA */
		};
		};
		};
		};

arch/arm64/boot/dts/qcom/sdm640-rumi.dtsi

+44 −0

Original line number	Diff line number	Diff line
		@@ -27,3 +27,47 @@
		&qupv3_se0_2uart {
		status = "ok";
		};

		&sdhc_1 {
		vdd-supply = <&pm640l_l11>;
		qcom,vdd-voltage-level = <2960000 2960000>;
		qcom,vdd-current-level = <200 570000>;

		vdd-io-supply = <&pm640_l12>;
		qcom,vdd-io-always-on;
		qcom,vdd-io-lpm-sup;
		qcom,vdd-io-voltage-level = <1800000 1800000>;
		qcom,vdd-io-current-level = <200 325000>;

		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
		pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;

		qcom,clk-rates = <400000 20000000 25000000 50000000>;
		qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";

		/delete-property/qcom,devfreq,freq-table;

		status = "ok";
		};

		&sdhc_2 {
		vdd-supply = <&pm640l_l9>;
		qcom,vdd-voltage-level = <2960000 2960000>;
		qcom,vdd-current-level = <200 800000>;

		vdd-io-supply = <&pm640l_l6>;
		qcom,vdd-io-voltage-level = <1800000 2950000>;
		qcom,vdd-io-current-level = <200 22000>;

		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
		pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;

		qcom,clk-rates = <400000 20000000 25000000 50000000>;
		qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50";

		/delete-property/qcom,devfreq,freq-table;

		status = "disabled";
		};

arch/arm64/boot/dts/qcom/sdm640.dtsi

+52 −0

Original line number	Diff line number	Diff line
		@@ -30,6 +30,8 @@

		aliases {
		serial0 = &qupv3_se0_2uart;
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
		};

		cpus {
		@@ -881,6 +883,56 @@
		compatible = "qcom,llcc-amon";
		};
		};

		sdhc_1: sdhci@7c4000 {
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;
		reg-names = "hc_mem", "cmdq_mem";

		interrupts = <0 641 0>, <0 644 0>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,bus-width = <8>;
		qcom,large-address-bus;

		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
		192000000 384000000>;
		qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";

		qcom,devfreq,freq-table = <50000000 200000000>;

		clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
		<&clock_gcc GCC_SDCC1_APPS_CLK>;
		clock-names = "iface_clk", "core_clk";

		qcom,nonremovable;
		status = "disabled";
		};

		sdhc_2: sdhci@8804000 {
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x8804000 0x1000>;
		reg-names = "hc_mem";

		interrupts = <0 204 0>, <0 222 0>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,bus-width = <4>;
		qcom,large-address-bus;

		qcom,clk-rates = <400000 20000000 25000000
		50000000 100000000 201500000>;
		qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
		"SDR104";

		qcom,devfreq,freq-table = <50000000 201500000>;

		clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
		<&clock_gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface_clk", "core_clk";

		status = "disabled";
		};
		};

		#include "sdm640-pinctrl.dtsi"