Merge "msm: ipa3: Added support for ipa 4.2 needed for SM6150" (81692ae4) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/devicetree/bindings/platform/msm/ipa.txt

+2 −0

Original line number	Diff line number	Diff line
		@@ -87,6 +87,8 @@ memory allocation over a PCIe bridge
		need to be unlocked by TZ.
		- qcom,ipa-uc-monitor-holb: Boolean context flag to indicate whether
		monitoring of holb via IPA uc is required.
		-qcom,ipa-fltrt-not-hashable: Boolean context flag to indicate filter/route rules
		hashing not supported.

		IPA pipe sub nodes (A2 static pipes configurations):

drivers/platform/msm/gsi/gsi.c

+14 −0

Original line number	Diff line number	Diff line
		@@ -709,6 +709,13 @@ static uint32_t gsi_get_max_channels(enum gsi_ver ver)
		GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK) >>
		GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT;
		break;
		case GSI_VER_2_2:
		reg = gsi_readl(gsi_ctx->base +
		GSI_V2_2_EE_n_GSI_HW_PARAM_2_OFFS(gsi_ctx->per.ee));
		reg = (reg &
		GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK) >>
		GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT;
		break;
		}

		GSIDBG("max channels %d\n", reg);
		@@ -752,6 +759,13 @@ static uint32_t gsi_get_max_event_rings(enum gsi_ver ver)
		GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK) >>
		GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT;
		break;
		case GSI_VER_2_2:
		reg = gsi_readl(gsi_ctx->base +
		GSI_V2_2_EE_n_GSI_HW_PARAM_2_OFFS(gsi_ctx->per.ee));
		reg = (reg &
		GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK) >>
		GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT;
		break;
		}

		GSIDBG("max event rings %d\n", reg);

drivers/platform/msm/gsi/gsi_reg.h

+32 −0

Original line number	Diff line number	Diff line
		@@ -1548,6 +1548,38 @@
		#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_N_HALF_KB_FVAL 0x2
		#define GSI_V2_0_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_KB_FVAL 0x3

		/* v2.2 */
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_OFFS(n) \
		(GSI_GSI_REG_BASE_OFFS + 0x0001f040 + 0x4000 * (n))
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_BMSK 0x8000
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_INTER_EE_SHFT 0xf
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_BMSK 0x4000
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_RD_WR_ENG_SHFT 0xE
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_RMSK 0x7fff
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_MAXn 2
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_BMSK 0x38000000
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_IOVEC_SHFT 0x1b
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_BMSK 0x7F80000
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_SDMA_MAX_BURST_SHFT 0x13
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_BMSK 0x70000
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_SDMA_N_INT_SHFT 0x10
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_BMSK 0x8000
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_USE_SDMA_SHFT 0xf
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_BMSK 0x4000
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_CH_FULL_LOGIC_SHFT 0xe
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_BMSK 0x2000
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_CH_PEND_TRANSLATE_SHFT 0xd
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_BMSK 0x1f00
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_NUM_EV_PER_EE_SHFT 0x8
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_BMSK 0xf8
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_NUM_CH_PER_EE_SHFT 0x3
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_BMSK 0x7
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_SHFT 0x0
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_ONE_KB_FVAL 0x0
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_KB_FVAL 0x1
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_TWO_N_HALF_KB_FVAL 0x2
		#define GSI_V2_2_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_KB_FVAL 0x3

		#define GSI_EE_n_GSI_SW_VERSION_OFFS(n) \
		(GSI_GSI_REG_BASE_OFFS + 0x0001f044 + 0x4000 * (n))
		#define GSI_EE_n_GSI_SW_VERSION_RMSK 0xffffffff

drivers/platform/msm/ipa/ipa_api.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -2797,6 +2797,10 @@ const char *ipa_get_version_string(enum ipa_hw_type ver)
		break;
		case IPA_HW_v4_1:
		str = "4.1";
		break;
		case IPA_HW_v4_2:
		str = "4.2";
		break;
		default:
		str = "Invalid version";
		break;
		@@ -2852,6 +2856,7 @@ static int ipa_generic_plat_drv_probe(struct platform_device *pdev_p)
		case IPA_HW_v3_5_1:
		case IPA_HW_v4_0:
		case IPA_HW_v4_1:
		case IPA_HW_v4_2:
		result = ipa3_plat_drv_probe(pdev_p, ipa_api_ctrl,
		ipa_plat_drv_match);
		break;

drivers/platform/msm/ipa/ipa_v3/ipa.c

+113 −29

Original line number	Diff line number	Diff line
		@@ -2122,6 +2122,9 @@ static void ipa3_q6_avoid_holb(void)
		ep_holb.tmr_val = 0;
		ep_holb.en = 1;

		if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_2)
		ipa3_cal_ep_holb_scale_base_val(ep_holb.tmr_val, &ep_holb);

		for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) {
		if (IPA_CLIENT_IS_Q6_CONS(client_idx)) {
		ep_idx = ipa3_get_ep_mapping(client_idx);
		@@ -2226,6 +2229,15 @@ static int ipa3_q6_clean_q6_flt_tbls(enum ipa_ip_type ip,
		return -EINVAL;
		}

		/*
		* SRAM memory not allocated to hash tables. Cleaning the of hash table
		* operation not supported.
		*/
		if (rlt == IPA_RULE_HASHABLE && ipa3_ctx->ipa_fltrt_not_hashable) {
		IPADBG("Clean hashable rules not supported\n");
		return retval;
		}

		/* Up to filtering pipes we have filtering tables */
		desc = kcalloc(ipa3_ctx->ep_flt_num, sizeof(struct ipa3_desc),
		GFP_KERNEL);
		@@ -2344,6 +2356,15 @@ static int ipa3_q6_clean_q6_rt_tbls(enum ipa_ip_type ip,
		return -EINVAL;
		}

		/*
		* SRAM memory not allocated to hash tables. Cleaning the of hash table
		* operation not supported.
		*/
		if (rlt == IPA_RULE_HASHABLE && ipa3_ctx->ipa_fltrt_not_hashable) {
		IPADBG("Clean hashable rules not supported\n");
		return retval;
		}

		if (ip == IPA_IP_v4) {
		modem_rt_index_lo = IPA_MEM_PART(v4_modem_rt_index_lo);
		modem_rt_index_hi = IPA_MEM_PART(v4_modem_rt_index_hi);
		@@ -2417,7 +2438,7 @@ static int ipa3_q6_clean_q6_tables(void)
		struct ipa3_desc *desc;
		struct ipahal_imm_cmd_pyld *cmd_pyld = NULL;
		struct ipahal_imm_cmd_register_write reg_write_cmd = {0};
		int retval;
		int retval = 0;
		struct ipahal_reg_fltrt_hash_flush flush;
		struct ipahal_reg_valmask valmask;

		@@ -2458,6 +2479,12 @@ static int ipa3_q6_clean_q6_tables(void)
		return -EFAULT;
		}

		/*
		* SRAM memory not allocated to hash tables. Cleaning the of hash table
		* operation not supported.
		*/
		if (ipa3_ctx->ipa_fltrt_not_hashable)
		return retval;
		/* Flush rules cache */
		desc = kzalloc(sizeof(struct ipa3_desc), GFP_KERNEL);
		if (!desc)
		@@ -2856,10 +2883,21 @@ int _ipa_init_rt4_v3(void)
		return rc;
		}

		/*
		* SRAM memory not allocated to hash tables. Initializing/Sending
		* command to hash tables(filer/routing) operation not supported.
		*/
		if (ipa3_ctx->ipa_fltrt_not_hashable) {
		v4_cmd.hash_rules_addr = 0;
		v4_cmd.hash_rules_size = 0;
		v4_cmd.hash_local_addr = 0;
		} else {
		v4_cmd.hash_rules_addr = mem.phys_base;
		v4_cmd.hash_rules_size = mem.size;
		v4_cmd.hash_local_addr = ipa3_ctx->smem_restricted_bytes +
		IPA_MEM_PART(v4_rt_hash_ofst);
		}

		v4_cmd.nhash_rules_addr = mem.phys_base;
		v4_cmd.nhash_rules_size = mem.size;
		v4_cmd.nhash_local_addr = ipa3_ctx->smem_restricted_bytes +
		@@ -2919,10 +2957,21 @@ int _ipa_init_rt6_v3(void)
		return rc;
		}

		/*
		* SRAM memory not allocated to hash tables. Initializing/Sending
		* command to hash tables(filer/routing) operation not supported.
		*/
		if (ipa3_ctx->ipa_fltrt_not_hashable) {
		v6_cmd.hash_rules_addr = 0;
		v6_cmd.hash_rules_size = 0;
		v6_cmd.hash_local_addr = 0;
		} else {
		v6_cmd.hash_rules_addr = mem.phys_base;
		v6_cmd.hash_rules_size = mem.size;
		v6_cmd.hash_local_addr = ipa3_ctx->smem_restricted_bytes +
		IPA_MEM_PART(v6_rt_hash_ofst);
		}

		v6_cmd.nhash_rules_addr = mem.phys_base;
		v6_cmd.nhash_rules_size = mem.size;
		v6_cmd.nhash_local_addr = ipa3_ctx->smem_restricted_bytes +
		@@ -2976,10 +3025,21 @@ int _ipa_init_flt4_v3(void)
		return rc;
		}

		/*
		* SRAM memory not allocated to hash tables. Initializing/Sending
		* command to hash tables(filer/routing) operation not supported.
		*/
		if (ipa3_ctx->ipa_fltrt_not_hashable) {
		v4_cmd.hash_rules_addr = 0;
		v4_cmd.hash_rules_size = 0;
		v4_cmd.hash_local_addr = 0;
		} else {
		v4_cmd.hash_rules_addr = mem.phys_base;
		v4_cmd.hash_rules_size = mem.size;
		v4_cmd.hash_local_addr = ipa3_ctx->smem_restricted_bytes +
		IPA_MEM_PART(v4_flt_hash_ofst);
		}

		v4_cmd.nhash_rules_addr = mem.phys_base;
		v4_cmd.nhash_rules_size = mem.size;
		v4_cmd.nhash_local_addr = ipa3_ctx->smem_restricted_bytes +
		@@ -3033,10 +3093,21 @@ int _ipa_init_flt6_v3(void)
		return rc;
		}

		/*
		* SRAM memory not allocated to hash tables. Initializing/Sending
		* command to hash tables(filer/routing) operation not supported.
		*/
		if (ipa3_ctx->ipa_fltrt_not_hashable) {
		v6_cmd.hash_rules_addr = 0;
		v6_cmd.hash_rules_size = 0;
		v6_cmd.hash_local_addr = 0;
		} else {
		v6_cmd.hash_rules_addr = mem.phys_base;
		v6_cmd.hash_rules_size = mem.size;
		v6_cmd.hash_local_addr = ipa3_ctx->smem_restricted_bytes +
		IPA_MEM_PART(v6_flt_hash_ofst);
		}

		v6_cmd.nhash_rules_addr = mem.phys_base;
		v6_cmd.nhash_rules_size = mem.size;
		v6_cmd.nhash_local_addr = ipa3_ctx->smem_restricted_bytes +
		@@ -3173,6 +3244,7 @@ static int ipa3_setup_apps_pipes(void)
		ipa3_ctx->ctrl->ipa_init_flt6();
		IPADBG("V6 FLT initialized\n");

		if (!ipa3_ctx->ipa_fltrt_not_hashable) {
		if (ipa3_setup_flt_hash_tuple()) {
		IPAERR(":fail to configure flt hash tuple\n");
		result = -EPERM;
		@@ -3186,7 +3258,7 @@ static int ipa3_setup_apps_pipes(void)
		goto fail_flt_hash_tuple;
		}
		IPADBG("rt hash tuple is configured\n");

		}
		if (ipa3_setup_exception_path()) {
		IPAERR(":fail to setup excp path\n");
		result = -EPERM;
		@@ -4389,6 +4461,9 @@ static enum gsi_ver ipa3_get_gsi_ver(enum ipa_hw_type ipa_hw_type)
		case IPA_HW_v4_1:
		gsi_ver = GSI_VER_2_0;
		break;
		case IPA_HW_v4_2:
		gsi_ver = GSI_VER_2_2;
		break;
		default:
		IPAERR("No GSI version for ipa type %d\n", ipa_hw_type);
		WARN_ON(1);
		@@ -5017,6 +5092,7 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
		ipa3_ctx->use_ipa_teth_bridge = resource_p->use_ipa_teth_bridge;
		ipa3_ctx->modem_cfg_emb_pipe_flt = resource_p->modem_cfg_emb_pipe_flt;
		ipa3_ctx->ipa_wdi2 = resource_p->ipa_wdi2;
		ipa3_ctx->ipa_fltrt_not_hashable = resource_p->ipa_fltrt_not_hashable;
		ipa3_ctx->use_64_bit_dma_mask = resource_p->use_64_bit_dma_mask;
		ipa3_ctx->wan_rx_ring_size = resource_p->wan_rx_ring_size;
		ipa3_ctx->lan_rx_ring_size = resource_p->lan_rx_ring_size;
		@@ -5566,6 +5642,7 @@ static int get_ipa_dts_configuration(struct platform_device *pdev,
		ipa_drv_res->ipa_tz_unlock_reg = NULL;
		ipa_drv_res->mhi_evid_limits[0] = IPA_MHI_GSI_EVENT_RING_ID_START;
		ipa_drv_res->mhi_evid_limits[1] = IPA_MHI_GSI_EVENT_RING_ID_END;
		ipa_drv_res->ipa_fltrt_not_hashable = false;

		/* Get IPA HW Version */
		result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-hw-ver",
		@@ -5639,6 +5716,13 @@ static int get_ipa_dts_configuration(struct platform_device *pdev,
		ipa_drv_res->ipa_wdi2
		? "True" : "False");

		ipa_drv_res->ipa_fltrt_not_hashable =
		of_property_read_bool(pdev->dev.of_node,
		"qcom,ipa-fltrt-not-hashable");
		IPADBG(": IPA filter/route rule hashable = %s\n",
		ipa_drv_res->ipa_fltrt_not_hashable
		? "True" : "False");

		ipa_drv_res->use_64_bit_dma_mask =
		of_property_read_bool(pdev->dev.of_node,
		"qcom,use-64-bit-dma-mask");