Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 814005c2 authored by Amit Nischal's avatar Amit Nischal Committed by Shefali Jain
Browse files

clk: qcom: Add CPU clock driver for QCS405 



Add support for QCS405 CPU clock driver for controlling
cpu clocks on QCS405.

Change-Id: Ie6344074dd3e7c1304af25efc0f5f570efeb8e0b
Signed-off-by: default avatarAmit Nischal <anischal@codeaurora.org>
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent ac121119

Documentation/devicetree/bindings/clock/qcom,qcs405-cpucc.txt

0 → 100644
+48 −0
Original line number Diff line number Diff line 
Qualcomm Technologies, Inc. QCS405 CPU clock driver

---------------------------------------------------



It is the clock controller driver which provides higher frequency

clocks and allows CPU frequency scaling on qcs405 based platforms.



Required properties:

- compatible:	Shall contain following:

		"qcom,cpu-qcs405"

- clocks:	Phandle to the clock device.

- clock-names:	Names of the used clocks. Shall contain following:

		"xo_ao", "gpll0_ao"

- reg:	Shall contain base register offset and size.

- reg-names:	Names of the bases for the above registers. Shall contain following:

		"apcs_cmd", "apcs_pll"

- vdd_dig_ao-supply:	The regulator powering the APSS PLL.

- cpu-vdd-supply:	The regulator powering the APSS RCG.

- qcom,speedX-bin-vZ:	A table of CPU frequency (Hz) to regulator voltage (uV) mapping.

			Format: <freq uV>

			This represents the max frequency possible for each possible

			power configuration for a CPU that's binned as speed bin X,

			speed bin revision Z. Version can be between [0-3].

- #clock-cells:	Shall contain 1.



Optional properties:

- reg-names:	"efuse"

- qcom,cpucc-init-rate:	Initial rate which needs to be set from cpu driver.



Example:

	clock_cpu: qcom,clock-cpu@0b011050 {

		compatible = "qcom,cpu-qcs405";

		clocks = <&clock_rpmcc RPM_SMD_XO_A_CLK_SRC>,

			<&clock_gcc GPLL0_AO_OUT_MAIN>;

		clock-names = "xo_ao", "gpll0_ao" ;

		qcom,cpucc-init-rate = <960000000>;

		reg = <0x0b011050 0x8>,

			<0xb016000 0x34>;

		reg-names = "apcs_cmd" , "apcs_pll";

		cpu-vdd-supply = <&apc_vreg_corner>;

		vdd_dig_ao-supply = <&pmd9655_s1_level>;

		qcom,speed0-bin-v0 =

			< 0         0>,

			< 960000000  1>,

			< 1113600000 2>,

			< 1267200000 3>,

			< 1382400000 4>;

		#clock-cells = <1>;

	};

drivers/clk/qcom/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -332,3 +332,12 @@ config MDM_DEBUGCC_QCS405 
	  Support for the debug clock controller on Qualcomm Technologies, Inc

	  QCS405 devices.

	  Say Y if you want to support the clock measurement functionality.



config CLOCK_CPU_QCS405

	bool "CPU QCS405 Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	 Support for the cpu clock controller on QCS405

	 based devices.

	 Say Y if you want to support CPU clock scaling using

	 CPUfreq drivers for dynamic power management.

drivers/clk/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o 
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o

obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o

obj-$(CONFIG_CLOCK_CPU_OSM) += clk-cpu-osm.o

obj-$(CONFIG_CLOCK_CPU_QCS405) += clk-cpu-qcs405.o

obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o

obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o

obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o

drivers/clk/qcom/clk-cpu-qcs405.c

0 → 100644
+763 −0

File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/qcom,cpu-qcs405.h

+4 −3
Original line number Diff line number Diff line
@@ -11,9 +11,10 @@ 
 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_MSM_CPU_CC_QCS405_H

#define _DT_BINDINGS_CLK_MSM_CPU_CC_QCS405_H

#ifndef _DT_BINDINGS_CLK_QCOM_CPU_QCS405_H

#define _DT_BINDINGS_CLK_QCOM_CPU_QCS405_H



#define A53_PERF_CL_CLK			0

#define APCS_CPU_PLL		0

#define APCS_MUX_CLK		1



#endif