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Commit 806c765e authored by Ivan T. Ivanov's avatar Ivan T. Ivanov Committed by Andy Gross
Browse files

arm64: dts: qcom: 8x16: UART1 add CTS_N, RTS_N pin configurations 



Add devicetree bindings for UART1 CTS_N and RTS_N pins.

Signed-off-by: default avatarIvan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: default avatarAndy Gross <agross@codeaurora.org>
parent 8005c49d

arch/arm64/boot/dts/qcom/msm8916-pins.dtsi

+9 −4
Original line number Original line Diff line number Diff line
@@ -16,10 +16,13 @@ 
	blsp1_uart1_default: blsp1_uart1_default {

	blsp1_uart1_default: blsp1_uart1_default {

		pinmux {

		pinmux {

			function = "blsp_uart1";

			function = "blsp_uart1";

			pins = "gpio0", "gpio1";

			//	TX, RX, CTS_N, RTS_N

			pins = "gpio0", "gpio1",

			       "gpio2", "gpio3";

		};

		};

		pinconf {

		pinconf {

			pins = "gpio0", "gpio1";

			pins = "gpio0", "gpio1",

			       "gpio2", "gpio3";

			drive-strength = <16>;

			drive-strength = <16>;

			bias-disable;

			bias-disable;

		};

		};
@@ -28,10 +31,12 @@ 
	blsp1_uart1_sleep: blsp1_uart1_sleep {

	blsp1_uart1_sleep: blsp1_uart1_sleep {

		pinmux {

		pinmux {

			function = "gpio";

			function = "gpio";

			pins = "gpio0", "gpio1";

			pins = "gpio0", "gpio1",

			       "gpio2", "gpio3";

		};

		};

		pinconf {

		pinconf {

			pins = "gpio0", "gpio1";

			pins = "gpio0", "gpio1",

			       "gpio2", "gpio3";

			drive-strength = <2>;

			drive-strength = <2>;

			bias-pull-down;

			bias-pull-down;

		};

		};