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Commit 8062b4aa authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.12' of... 

Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock patches for 4.12 from Maxime Ripard:

Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.

* tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: Display index when clock registration fails
  clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
  clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
  clk: sunxi-ng: mult: Support PLL lock detection
  clk: sunxi-ng: add support for PRCM CCUs
  dt-bindings: update device tree binding for Allwinner PRCM CCUs
  clk: sunxi-ng: sun5i: Fix mux width for csi clock
  clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
  clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
  clk: sunxi-ng: gate: Support common pre-dividers
parents e609f9f2 cb545960

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+17 −1
Original line number Diff line number Diff line
@@ -7,9 +7,12 @@ Required properties : 
		- "allwinner,sun8i-a23-ccu"

		- "allwinner,sun8i-a33-ccu"

		- "allwinner,sun8i-h3-ccu"

		- "allwinner,sun8i-h3-r-ccu"

		- "allwinner,sun8i-v3s-ccu"

		- "allwinner,sun9i-a80-ccu"

		- "allwinner,sun50i-a64-ccu"

		- "allwinner,sun50i-a64-r-ccu"

		- "allwinner,sun50i-h5-ccu"



- reg: Must contain the registers base address and length

- clocks: phandle to the oscillators feeding the CCU. Two are needed:
@@ -19,7 +22,10 @@ Required properties : 
- #clock-cells : must contain 1

- #reset-cells : must contain 1



Example:

For the PRCM CCUs on H3/A64, one more clock is needed:

- "iosc": the SoC's internal frequency oscillator



Example for generic CCU:

ccu: clock@01c20000 {

	compatible = "allwinner,sun8i-h3-ccu";

	reg = <0x01c20000 0x400>;
@@ -28,3 +34,13 @@ ccu: clock@01c20000 { 
	#clock-cells = <1>;

	#reset-cells = <1>;

};



Example for PRCM CCU:

r_ccu: clock@01f01400 {

	compatible = "allwinner,sun50i-a64-r-ccu";

	reg = <0x01f01400 0x100>;

	clocks = <&osc24M>, <&osc32k>, <&iosc>;

	clock-names = "hosc", "losc", "iosc";

	#clock-cells = <1>;

	#reset-cells = <1>;

};

drivers/clk/sunxi-ng/Kconfig

+15 −1
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ config SUN50I_A64_CCU 
	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN5I_CCU

	bool "Support for the Allwinner sun5i family CCM"
@@ -75,6 +76,7 @@ config SUN5I_CCU 
	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN5I

	depends on MACH_SUN5I || COMPILE_TEST



config SUN6I_A31_CCU

	bool "Support for the Allwinner A31/A31s CCU"
@@ -86,6 +88,7 @@ config SUN6I_A31_CCU 
	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN6I

	depends on MACH_SUN6I || COMPILE_TEST



config SUN8I_A23_CCU

	bool "Support for the Allwinner A23 CCU"
@@ -98,6 +101,7 @@ config SUN8I_A23_CCU 
	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN8I

	depends on MACH_SUN8I || COMPILE_TEST



config SUN8I_A33_CCU

	bool "Support for the Allwinner A33 CCU"
@@ -110,6 +114,7 @@ config SUN8I_A33_CCU 
	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN8I

	depends on MACH_SUN8I || COMPILE_TEST



config SUN8I_H3_CCU

	bool "Support for the Allwinner H3 CCU"
@@ -120,7 +125,8 @@ config SUN8I_H3_CCU 
	select SUNXI_CCU_NM

	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN8I

	default MACH_SUN8I || (ARM64 && ARCH_SUNXI)

	depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN8I_V3S_CCU

	bool "Support for the Allwinner V3s CCU"
@@ -132,6 +138,7 @@ config SUN8I_V3S_CCU 
	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN8I

	depends on MACH_SUN8I || COMPILE_TEST



config SUN9I_A80_CCU

	bool "Support for the Allwinner A80 CCU"
@@ -143,5 +150,12 @@ config SUN9I_A80_CCU 
	select SUNXI_CCU_MP

	select SUNXI_CCU_PHASE

	default MACH_SUN9I

	depends on MACH_SUN9I || COMPILE_TEST



config SUN8I_R_CCU

	bool "Support for Allwinner SoCs' PRCM CCUs"

	select SUNXI_CCU_DIV

	select SUNXI_CCU_GATE

	default MACH_SUN8I || (ARCH_SUNXI && ARM64)



endif

drivers/clk/sunxi-ng/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o 
obj-$(CONFIG_SUN8I_A33_CCU)	+= ccu-sun8i-a33.o

obj-$(CONFIG_SUN8I_H3_CCU)	+= ccu-sun8i-h3.o

obj-$(CONFIG_SUN8I_V3S_CCU)	+= ccu-sun8i-v3s.o

obj-$(CONFIG_SUN8I_R_CCU)	+= ccu-sun8i-r.o

obj-$(CONFIG_SUN9I_A80_CCU)	+= ccu-sun9i-a80.o

obj-$(CONFIG_SUN9I_A80_CCU)	+= ccu-sun9i-a80-de.o

obj-$(CONFIG_SUN9I_A80_CCU)	+= ccu-sun9i-a80-usb.o

drivers/clk/sunxi-ng/ccu-sun5i.c

+1 −1
Original line number Diff line number Diff line
@@ -469,7 +469,7 @@ static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1", 
static const u8 csi_table[] = { 0, 1, 2, 5, 6 };

static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",

				       csi_parents, csi_table,

				       0x134, 0, 5, 24, 2, BIT(31), 0);

				       0x134, 0, 5, 24, 3, BIT(31), 0);



static SUNXI_CCU_GATE(ve_clk,		"ve",		"pll-ve",

		      0x13c, BIT(31), CLK_SET_RATE_PARENT);

drivers/clk/sunxi-ng/ccu-sun8i-a33.c

+11 −7
Original line number Diff line number Diff line
@@ -159,13 +159,17 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 
					BIT(28),	/* lock */

					CLK_SET_RATE_UNGATE);



/* TODO: Fix N */

static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",

				  "osc24M", 0x04c,

				  8, 6,			/* N */

				  BIT(31),		/* gate */

				  BIT(28),		/* lock */

				  CLK_SET_RATE_UNGATE);

static struct ccu_mult pll_ddr1_clk = {

	.enable	= BIT(31),

	.lock	= BIT(28),

	.mult	= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),

	.common	= {

		.reg		= 0x04c,

		.hw.init	= CLK_HW_INIT("pll-ddr1", "osc24M",

					      &ccu_mult_ops,

					      CLK_SET_RATE_UNGATE),

	},

};



static const char * const cpux_parents[] = { "osc32k", "osc24M",

					     "pll-cpux" , "pll-cpux" };