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Commit 804a5dd6 authored by Joachim Eastwood's avatar Joachim Eastwood Committed by Arnd Bergmann
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ARM: dts: Add base DT for NXP LPC18xx 



NXP LPC18xx/43xx SoCs are very similar devices and should be able to
share a common base (lpc18xx.dtsi). Diffences between the devices are
put in a dtsi which is specific to that device.

Signed-off-by: default avatarJoachim Eastwood <manabian@gmail.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent ca9341d4

arch/arm/boot/dts/lpc18xx.dtsi

0 → 100644
+114 −0
Original line number Diff line number Diff line 
/*

 * Common base for NXP LPC18xx and LPC43xx devices.

 *

 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>

 *

 * This code is released using a dual license strategy: BSD/GPL

 * You can choose the licence that better fits your requirements.

 *

 * Released under the terms of 3-clause BSD License

 * Released under the terms of GNU General Public License Version 2.0

 *

 */



#include "armv7-m.dtsi"



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "arm,cortex-m3";

			device_type = "cpu";

			reg = <0x0>;

		};

	};



	clocks {

		xtal: xtal {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <12000000>;

		};



		/* Temporary hardcode PLL1 until clk drivers are merged */

		pll1: pll1 {

			compatible = "fixed-factor-clock";

			clocks = <&xtal>;

			#clock-cells = <0>;

			clock-div = <1>;

			clock-mult = <12>;

		};

	};



	soc {

		uart0: serial@40081000 {

			compatible = "ns16550a";

			reg = <0x40081000 0x1000>;

			reg-shift = <2>;

			interrupts = <24>;

			clocks = <&pll1>;

			status = "disabled";

		};



		uart1: serial@40082000 {

			compatible = "ns16550a";

			reg = <0x40082000 0x1000>;

			reg-shift = <2>;

			interrupts = <25>;

			clocks = <&pll1>;

			status = "disabled";

		};



		timer0: timer@40084000 {

			compatible = "nxp,lpc3220-timer";

			reg = <0x40084000 0x1000>;

			interrupts = <12>;

			clocks = <&pll1>;

			clock-names = "timerclk";

		};



		timer1: timer@40085000 {

			compatible = "nxp,lpc3220-timer";

			reg = <0x40085000 0x1000>;

			interrupts = <13>;

			clocks = <&pll1>;

			clock-names = "timerclk";

		};



		uart2: serial@400c1000 {

			compatible = "ns16550a";

			reg = <0x400c1000 0x1000>;

			reg-shift = <2>;

			interrupts = <26>;

			clocks = <&pll1>;

			status = "disabled";

		};



		uart3: serial@400c2000 {

			compatible = "ns16550a";

			reg = <0x400c2000 0x1000>;

			reg-shift = <2>;

			interrupts = <27>;

			clocks = <&pll1>;

			status = "disabled";

		};



		timer2: timer@400c3000 {

			compatible = "nxp,lpc3220-timer";

			reg = <0x400c3000 0x1000>;

			interrupts = <14>;

			clocks = <&pll1>;

			clock-names = "timerclk";

		};



		timer3: timer@400c4000 {

			compatible = "nxp,lpc3220-timer";

			reg = <0x400c4000 0x1000>;

			interrupts = <15>;

			clocks = <&pll1>;

			clock-names = "timerclk";

		};

	};

};