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Commit 8020cf10 authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Introduce bus topology for ATOLL 



Bus topology is the representation of bus connections
in SOC and is required for bus scaling driver to serve
the bandwidth requests from clients.

Change-Id: Ib7204524da5ab8a752a64426fc7ac8e3b139034a
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent dc9a2b8f

arch/arm64/boot/dts/qcom/atoll-bus.dtsi

0 → 100644
+1994 −0

File added.

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arch/arm64/boot/dts/qcom/atoll.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -2249,6 +2249,7 @@ 
#include "msm-arm-smmu-atoll.dtsi"

#include "atoll-qupv3.dtsi"

#include "sdmmagpie-gpu.dtsi"

#include "atoll-bus.dtsi"



&msm_gpu {

	/delete-property/qcom,gpu-speed-bin;

include/dt-bindings/msm/msm-bus-ids.h

+28 −11
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
#define	MSM_BUS_FAB_GPU_VIRT 6158

#define	MSM_BUS_FAB_MMNRT_VIRT 6159

#define	MSM_BUS_FAB_MMRT_VIRT 6160

#define	MSM_BUS_FAB_NPU_NOC 6161



#define	MSM_BUS_FAB_MC_VIRT_DISPLAY 26000

#define	MSM_BUS_FAB_MEM_NOC_DISPLAY 26001
@@ -100,16 +101,17 @@ 
#define	MSM_BUS_BCM_CO0 7041

#define	MSM_BUS_BCM_CO1 7042

#define	MSM_BUS_BCM_CO2 7043

#define	MSM_BUS_BCM_QP0 7044

#define	MSM_BUS_BCM_PN0 7045

#define	MSM_BUS_BCM_PN1 7046

#define	MSM_BUS_BCM_PN2 7047

#define	MSM_BUS_BCM_PN3 7048

#define	MSM_BUS_BCM_PN4 7049

#define	MSM_BUS_BCM_PN5 7050

#define	MSM_BUS_BCM_SH8 7051

#define	MSM_BUS_BCM_SH9 7052

#define	MSM_BUS_BCM_SH10 7053

#define	MSM_BUS_BCM_CO3 7044

#define	MSM_BUS_BCM_QP0 7045

#define	MSM_BUS_BCM_PN0 7046

#define	MSM_BUS_BCM_PN1 7047

#define	MSM_BUS_BCM_PN2 7048

#define	MSM_BUS_BCM_PN3 7049

#define	MSM_BUS_BCM_PN4 7050

#define	MSM_BUS_BCM_PN5 7051

#define	MSM_BUS_BCM_SH8 7052

#define	MSM_BUS_BCM_SH9 7053

#define	MSM_BUS_BCM_SH10 7054



#define	MSM_BUS_RSC_APPS 8000

#define	MSM_BUS_RSC_DISP 8001
@@ -308,6 +310,8 @@ 
#define	MSM_BUS_MASTER_GPU_CDSP_PROC 182

#define	MSM_BUS_MASTER_QUP_CORE_0 183

#define	MSM_BUS_MASTER_QUP_CORE_1 184

#define	MSM_BUS_MASTER_NPU_PROC 185

#define	MSM_BUS_MASTER_NPU_SYS 186



#define	MSM_BUS_MASTER_LLCC_DISPLAY 20000

#define	MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY 20001
@@ -699,6 +703,19 @@ 
#define	MSM_BUS_SLAVE_GPU_CDSP_BIMC 820

#define	MSM_BUS_SLAVE_QM_MPU_CFG 821

#define	MSM_BUS_SLAVE_CDSP_THROTTLE_CFG 822

#define	MSM_BUS_MASTER_NPU_NOC_CFG 823

#define	MSM_BUS_SLAVE_NPU_CAL_DP0 824

#define	MSM_BUS_SLAVE_NPU_CP 825

#define	MSM_BUS_SLAVE_NPU_INT_DMA_BWMON_CFG 826

#define	MSM_BUS_SLAVE_NPU_DPM 827

#define	MSM_BUS_SLAVE_ISENSE_CFG 828

#define	MSM_BUS_SLAVE_NPU_LLM_CFG 829

#define	MSM_BUS_SLAVE_NPU_TCM 830

#define	MSM_BUS_SLAVE_NPU_COMPUTE_NOC 831

#define	MSM_BUS_SLAVE_SERVICE_NPU_NOC 832

#define	MSM_BUS_SLAVE_DISPLAY_RT_THROTTLE_CFG 833

#define	MSM_BUS_SLAVE_NPU_DMA_BWMON_CFG 834

#define	MSM_BUS_SLAVE_NPU_PROC_BWMON_CFG 835



#define	MSM_BUS_SLAVE_EBI_CH0_DISPLAY 20512

#define	MSM_BUS_SLAVE_LLCC_DISPLAY 20513