Merge branch 'for-4.10/firmware' into for-4.10/reset

NVIDIA Tegra Boot and Power Management Processor (BPMP)

The BPMP is a specific processor in Tegra chip, which is designed for

booting process handling and offloading the power management, clock

management, and reset control tasks from the CPU. The binding document

defines the resources that would be used by the BPMP firmware driver,

which can create the interprocessor communication (IPC) between the CPU

and BPMP.

Required properties:

- name : Should be bpmp

- compatible

    Array of strings

    One of:

    - "nvidia,tegra186-bpmp"

- mboxes : The phandle of mailbox controller and the mailbox specifier.

- shmem : List of the phandle of the TX and RX shared memory area that

	  the IPC between CPU and BPMP is based on.

- #clock-cells : Should be 1.

- #power-domain-cells : Should be 1.

- #reset-cells : Should be 1.

This node is a mailbox consumer. See the following files for details of

the mailbox subsystem, and the specifiers implemented by the relevant

provider(s):

- .../mailbox/mailbox.txt

- .../mailbox/nvidia,tegra186-hsp.txt

This node is a clock, power domain, and reset provider. See the following

files for general documentation of those features, and the specifiers

implemented by this node:

- .../clock/clock-bindings.txt

- <dt-bindings/clock/tegra186-clock.h>

- ../power/power_domain.txt

- <dt-bindings/power/tegra186-powergate.h>

- .../reset/reset.txt

- <dt-bindings/reset/tegra186-reset.h>

The BPMP implements some services which must be represented by separate nodes.

For example, it can provide access to certain I2C controllers, and the I2C

bindings represent each I2C controller as a device tree node. Such nodes should

be nested directly inside the main BPMP node.

Software can determine whether a child node of the BPMP node represents a device

by checking for a compatible property. Any node with a compatible property

represents a device that can be instantiated. Nodes without a compatible

property may be used to provide configuration information regarding the BPMP

itself, although no such configuration nodes are currently defined by this

binding.

The BPMP firmware defines no single global name-/numbering-space for such

services. Put another way, the numbering scheme for I2C buses is distinct from

the numbering scheme for any other service the BPMP may provide (e.g. a future

hypothetical SPI bus service). As such, child device nodes will have no reg

property, and the BPMP node will have no #address-cells or #size-cells property.

The shared memory bindings for BPMP

-----------------------------------

The shared memory area for the IPC TX and RX between CPU and BPMP are

predefined and work on top of sysram, which is an SRAM inside the chip.

See ".../sram/sram.txt" for the bindings.

Example:

hsp_top0: hsp@03c00000 {

	...

	#mbox-cells = <2>;

};

sysram@30000000 {

	compatible = "nvidia,tegra186-sysram", "mmio-sram";

	reg = <0x0 0x30000000 0x0 0x50000>;

	#address-cells = <2>;

	#size-cells = <2>;

	ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;

	cpu_bpmp_tx: shmem@4e000 {

		compatible = "nvidia,tegra186-bpmp-shmem";

		reg = <0x0 0x4e000 0x0 0x1000>;

		label = "cpu-bpmp-tx";

		pool;

	};

	cpu_bpmp_rx: shmem@4f000 {

		compatible = "nvidia,tegra186-bpmp-shmem";

		reg = <0x0 0x4f000 0x0 0x1000>;

		label = "cpu-bpmp-rx";

		pool;

	};

};

bpmp {

	compatible = "nvidia,tegra186-bpmp";

	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;

	shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;

	#clock-cells = <1>;

	#power-domain-cells = <1>;

	#reset-cells = <1>;

	i2c {

		compatible = "...";

		...

	};

};

NVIDIA Tegra Hardware Synchronization Primitives (HSP)

The HSP modules are used for the processors to share resources and communicate

together. It provides a set of hardware synchronization primitives for

interprocessor communication. So the interprocessor communication (IPC)

protocols can use hardware synchronization primitives, when operating between

two processors not in an SMP relationship.

The features that HSP supported are shared mailboxes, shared semaphores,

arbitrated semaphores and doorbells.

Required properties:

- name : Should be hsp

- compatible

    Array of strings.

    one of:

    - "nvidia,tegra186-hsp"

- reg : Offset and length of the register set for the device.

- interrupt-names

    Array of strings.

    Contains a list of names for the interrupts described by the interrupt

    property. May contain the following entries, in any order:

    - "doorbell"

    Users of this binding MUST look up entries in the interrupt property

    by name, using this interrupt-names property to do so.

- interrupts

    Array of interrupt specifiers.

    Must contain one entry per entry in the interrupt-names property,

    in a matching order.

- #mbox-cells : Should be 2.

The mbox specifier of the "mboxes" property in the client node should

contain two data. The first one should be the HSP type and the second

one should be the ID that the client is going to use. Those information

can be found in the following file.

- <dt-bindings/mailbox/tegra186-hsp.h>.

Example:

hsp_top0: hsp@3c00000 {

	compatible = "nvidia,tegra186-hsp";

	reg = <0x0 0x03c00000 0x0 0xa0000>;

	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "doorbell";

	#mbox-cells = <2>;

};

client {

	...

	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>;

};

source "drivers/firmware/google/Kconfig"

source "drivers/firmware/efi/Kconfig"

source "drivers/firmware/meson/Kconfig"

source "drivers/firmware/tegra/Kconfig"

endmenu

obj-$(CONFIG_GOOGLE_FIRMWARE)	+= google/

obj-$(CONFIG_EFI)		+= efi/

obj-$(CONFIG_UEFI_CPER)		+= efi/

obj-y				+= tegra/

menu "Tegra firmware driver"

config TEGRA_IVC

	bool "Tegra IVC protocol"

	depends on ARCH_TEGRA

	help

	  IVC (Inter-VM Communication) protocol is part of the IPC

	  (Inter Processor Communication) framework on Tegra. It maintains the

	  data and the different commuication channels in SysRAM or RAM and

	  keeps the content is synchronization between host CPU and remote

	  processors.

config TEGRA_BPMP

	bool "Tegra BPMP driver"

	depends on ARCH_TEGRA && TEGRA_HSP_MBOX && TEGRA_IVC

	help

	  BPMP (Boot and Power Management Processor) is designed to off-loading

	  the PM functions which include clock/DVFS/thermal/power from the CPU.

	  It needs HSP as the HW synchronization and notification module and

	  IVC module as the message communication protocol.

	  This driver manages the IPC interface between host CPU and the

	  firmware running on BPMP.

endmenu