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Commit 7fd5216a authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: qcom: Enforce ordering between the GCC and multimedia CC drivers 



On SDM855, the DISPCC, CAMCC, and VIDEOCC registers are inaccessible
until the GCC driver probes and enables the relevant multimedia AHB
clocks. Enforce this order by getting the AHB clock handles from the
respective multimedia clock controllers explicitly.

Change-Id: I3e2390207f445799f8610bb82d7e4d4d89650866
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 058dad3c

Documentation/devicetree/bindings/clock/qcom,camcc.txt

+5 −3
Original line number Diff line number Diff line
@@ -6,10 +6,10 @@ Required properties : 
- reg : shall contain base register location and length.

- reg-names: names of registers listed in the same order as in

	     the reg property.

- #clock-cells : shall contain 1.



Optional properties :

- clock-names: Shall contain "cfg_ahb_clk"

- clocks: phandle + clock reference to the GCC AHB clock.

- vdd_<rail>-supply: The logic rail supply.

- #clock-cells : shall contain 1.



Example:

	clock_camcc: qcom,camcc {
@@ -18,5 +18,7 @@ Example: 
		reg-names = "cc_base";

		vdd_mx-supply = <&pm855l_s4_level>;

		vdd_mm-supply = <&pm855l_s5_level>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

		#clock-cells = <1>;

	};

Documentation/devicetree/bindings/clock/qcom,dispcc.txt

+4 −0
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ Required properties : 
- reg-names: Address name. Must be "cc_base".

- vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf

		 of the clocks.

- clock-names: Shall contain "cfg_ahb_clk"

- clocks: phandle + clock reference to the GCC AHB clock.

- #clock-cells : Shall contain 1.

- #reset-cells : Shall contain 1.
@@ -16,6 +18,8 @@ Example: 
		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

Documentation/devicetree/bindings/clock/qcom,videocc.txt

+5 −3
Original line number Diff line number Diff line
@@ -4,18 +4,20 @@ Required properties: 
- compatible: shall contain "qcom,videocc-sdm855".

- reg: shall contain base register location and length.

- reg-names: names of registers listed in the same order as in the reg property.

- vdd_mm-supply: the logic rail supply.

- clock-names: Shall contain "cfg_ahb_clk"

- clocks: phandle + clock reference to the GCC AHB clock.

- #clock-cells: shall contain 1.

- #reset-cells: shall contain 1.



Optional properties:

- vdd_<rail>-supply: the logic rail supply.



Example:

	qcom,videocc@ab00000 {

		compatible = "qcom,videocc-sdm855";

		reg = <0xab00000 0x10000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

arch/arm64/boot/dts/qcom/sdm855.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -705,6 +705,8 @@ 
		reg = <0xab00000 0x10000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -715,6 +717,8 @@ 
		reg-names = "cc_base";

		vdd_mx-supply = <&pm855l_s4_level>;

		vdd_mm-supply = <&pm855l_s5_level>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

		#clock-cells = <1>;

	};
@@ -723,6 +727,8 @@ 
		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

drivers/clk/qcom/camcc-sdm855.c

+9 −0
Original line number Diff line number Diff line
@@ -2265,6 +2265,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sdm855_match_table); 
static int cam_cc_sdm855_probe(struct platform_device *pdev)

{

	struct regmap *regmap;

	struct clk *clk;

	int ret = 0;



	regmap = qcom_cc_map(pdev, &cam_cc_sdm855_desc);
@@ -2273,6 +2274,14 @@ static int cam_cc_sdm855_probe(struct platform_device *pdev) 
		return PTR_ERR(regmap);

	}



	clk = devm_clk_get(&pdev->dev, "cfg_ahb_clk");

	if (IS_ERR(clk)) {

		if (PTR_ERR(clk) != -EPROBE_DEFER)

			dev_err(&pdev->dev, "Unable to get ahb clock handle\n");

		return PTR_ERR(clk);

	}

	devm_clk_put(&pdev->dev, clk);



	vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");

	if (IS_ERR(vdd_mx.regulator[0])) {

		if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)