Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7f1f3851 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

drm/i915: sprite support for ValleyView v4



No constant alpha yet though, that needs a new ioctl and/or property to
get/set.

v2: use drm_plane_format_cpp (Ville)
    fix up vlv_disable_plane, remove IVB bits (Ville)
    remove error path rework (Ville)
    fix component order confusion (Ville)
    clean up platform init (Ville)
    use compute_offset_xtiled (Ville)
v3: fix up more format confusion (Ville)
    update to new page offset function (Ville)
v4: remove incorrect formats from framebuffer_init (Ville)

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 22f9fe50
Loading
Loading
Loading
Loading
+4 −0
Original line number Original line Diff line number Diff line
@@ -1630,6 +1630,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
	mutex_init(&dev_priv->rps.hw_lock);
	mutex_init(&dev_priv->rps.hw_lock);
	mutex_init(&dev_priv->modeset_restore_lock);
	mutex_init(&dev_priv->modeset_restore_lock);


	dev_priv->num_plane = 1;
	if (IS_VALLEYVIEW(dev))
		dev_priv->num_plane = 2;

	ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
	ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
	if (ret)
	if (ret)
		goto out_gem_unload;
		goto out_gem_unload;
+1 −0
Original line number Original line Diff line number Diff line
@@ -926,6 +926,7 @@ typedef struct drm_i915_private {
	bool enable_hotplug_processing;
	bool enable_hotplug_processing;


	int num_pch_pll;
	int num_pch_pll;
	int num_plane;


	unsigned long cfb_size;
	unsigned long cfb_size;
	unsigned int cfb_fb;
	unsigned int cfb_fb;
+57 −0
Original line number Original line Diff line number Diff line
@@ -3288,6 +3288,63 @@
#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)


#define _SPACNTR		0x72180
#define   SP_ENABLE			(1<<31)
#define   SP_GEAMMA_ENABLE		(1<<30)
#define   SP_PIXFORMAT_MASK		(0xf<<26)
#define   SP_FORMAT_YUV422		(0<<26)
#define   SP_FORMAT_BGR565		(5<<26)
#define   SP_FORMAT_BGRX8888		(6<<26)
#define   SP_FORMAT_BGRA8888		(7<<26)
#define   SP_FORMAT_RGBX1010102		(8<<26)
#define   SP_FORMAT_RGBA1010102		(9<<26)
#define   SP_FORMAT_RGBX8888		(0xe<<26)
#define   SP_FORMAT_RGBA8888		(0xf<<26)
#define   SP_SOURCE_KEY			(1<<22)
#define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
#define   SP_YUV_ORDER_YUYV		(0<<16)
#define   SP_YUV_ORDER_UYVY		(1<<16)
#define   SP_YUV_ORDER_YVYU		(2<<16)
#define   SP_YUV_ORDER_VYUY		(3<<16)
#define   SP_TILED			(1<<10)
#define _SPALINOFF		0x72184
#define _SPASTRIDE		0x72188
#define _SPAPOS			0x7218c
#define _SPASIZE		0x72190
#define _SPAKEYMINVAL		0x72194
#define _SPAKEYMSK		0x72198
#define _SPASURF		0x7219c
#define _SPAKEYMAXVAL		0x721a0
#define _SPATILEOFF		0x721a4
#define _SPACONSTALPHA		0x721a8
#define _SPAGAMC		0x721f4

#define _SPBCNTR		0x72280
#define _SPBLINOFF		0x72284
#define _SPBSTRIDE		0x72288
#define _SPBPOS			0x7228c
#define _SPBSIZE		0x72290
#define _SPBKEYMINVAL		0x72294
#define _SPBKEYMSK		0x72298
#define _SPBSURF		0x7229c
#define _SPBKEYMAXVAL		0x722a0
#define _SPBTILEOFF		0x722a4
#define _SPBCONSTALPHA		0x722a8
#define _SPBGAMC		0x722f4

#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)

/* VBIOS regs */
/* VBIOS regs */
#define VGACNTRL		0x71400
#define VGACNTRL		0x71400
# define VGA_DISP_DISABLE			(1 << 31)
# define VGA_DISP_DISABLE			(1 << 31)
+7 −4
Original line number Original line Diff line number Diff line
@@ -8867,7 +8867,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
void intel_modeset_init(struct drm_device *dev)
void intel_modeset_init(struct drm_device *dev)
{
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i, ret;
	int i, j, ret;


	drm_mode_config_init(dev);
	drm_mode_config_init(dev);


@@ -8903,9 +8903,12 @@ void intel_modeset_init(struct drm_device *dev)


	for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
	for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
		intel_crtc_init(dev, i);
		intel_crtc_init(dev, i);
		ret = intel_plane_init(dev, i);
		for (j = 0; j < dev_priv->num_plane; j++) {
			ret = intel_plane_init(dev, i, j);
			if (ret)
			if (ret)
			DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
				DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
					      i, j, ret);
		}
	}
	}


	intel_cpu_pll_init(dev);
	intel_cpu_pll_init(dev);
+2 −1
Original line number Original line Diff line number Diff line
@@ -241,6 +241,7 @@ struct intel_crtc {


struct intel_plane {
struct intel_plane {
	struct drm_plane base;
	struct drm_plane base;
	int plane;
	enum pipe pipe;
	enum pipe pipe;
	struct drm_i915_gem_object *obj;
	struct drm_i915_gem_object *obj;
	bool can_scale;
	bool can_scale;
@@ -489,7 +490,7 @@ extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern int intel_edp_target_clock(struct intel_encoder *,
extern int intel_edp_target_clock(struct intel_encoder *,
				  struct drm_display_mode *mode);
				  struct drm_display_mode *mode);
extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
				      enum plane plane);
				      enum plane plane);


Loading