Loading drivers/gpu/msm/adreno_a6xx.c +3 −3 Original line number Diff line number Diff line Loading @@ -1597,7 +1597,7 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS) | gpu_scid; if (adreno_is_a640(adreno_dev)) { if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) { kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1, A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val); } else { Loading @@ -1619,7 +1619,7 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) * On A640, the GPUHTW SCID is configured via a NoC override in the * XBL image. */ if (adreno_is_a640(adreno_dev)) if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) return; gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice); Loading @@ -1640,7 +1640,7 @@ static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev) * Attributes override through GBIF is not supported with MMU-500. * Attributes are used as configured through SMMU pagetable entries. */ if (adreno_is_a640(adreno_dev)) if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) return; /* Loading drivers/gpu/msm/kgsl_iommu.c +1 −1 Original line number Diff line number Diff line Loading @@ -1182,7 +1182,7 @@ void _enable_gpuhtw_llc(struct kgsl_mmu *mmu, struct kgsl_iommu_pt *iommu_pt) return; /* Domain attribute to enable system cache for GPU pagetable walks */ if (adreno_is_a640(adreno_dev)) if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) ret = iommu_domain_set_attr(iommu_pt->domain, DOMAIN_ATTR_USE_LLC_NWA, &gpuhtw_llc_enable); else Loading Loading
drivers/gpu/msm/adreno_a6xx.c +3 −3 Original line number Diff line number Diff line Loading @@ -1597,7 +1597,7 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS) | gpu_scid; if (adreno_is_a640(adreno_dev)) { if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) { kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1, A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val); } else { Loading @@ -1619,7 +1619,7 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) * On A640, the GPUHTW SCID is configured via a NoC override in the * XBL image. */ if (adreno_is_a640(adreno_dev)) if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) return; gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice); Loading @@ -1640,7 +1640,7 @@ static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev) * Attributes override through GBIF is not supported with MMU-500. * Attributes are used as configured through SMMU pagetable entries. */ if (adreno_is_a640(adreno_dev)) if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) return; /* Loading
drivers/gpu/msm/kgsl_iommu.c +1 −1 Original line number Diff line number Diff line Loading @@ -1182,7 +1182,7 @@ void _enable_gpuhtw_llc(struct kgsl_mmu *mmu, struct kgsl_iommu_pt *iommu_pt) return; /* Domain attribute to enable system cache for GPU pagetable walks */ if (adreno_is_a640(adreno_dev)) if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) ret = iommu_domain_set_attr(iommu_pt->domain, DOMAIN_ATTR_USE_LLC_NWA, &gpuhtw_llc_enable); else Loading