Commit 7e81bda2 authored Sep 15, 2016 by Chen-Yu Tsai Committed by Maxime Ripard Sep 18, 2016

drm/sun4i: dotclock: Allow divider = 127



The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127,
or 6 ~ 127 if phase offsets are used. The 0 register value also
represents a divider of 1 or bypass.

Make the end condition of the for loop inclusive of 127 in the
round_rate callback.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent e996e208

drivers/gpu/drm/sun4i/sun4i_dotclock.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -77,7 +77,7 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
		u8 best_div = 1;
		int i;

		for (i = 6; i < 127; i++) {
		for (i = 6; i <= 127; i++) {
		unsigned long ideal = rate * i;
		unsigned long rounded;