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Commit 7e70b074 authored by Subbaraman Narayanamurthy's avatar Subbaraman Narayanamurthy
Browse files

power: qpnp-fg-gen4: Add support to configure thermistor pull up 



Battery thermistor pull up resistor configuration for GEN4 FG
comes from battery profile. Add support to read the property
from the battery profile and configure it.

Change-Id: Ib63047c8d141339443770c8e4dcc980f8b12007a
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent f6e40f20

Documentation/devicetree/bindings/batterydata/batterydata.txt

+2 −0
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ Profile data node optional properties: 
			size 5.

- qcom,therm-center-offset: Specifies the resistor divide ratio between pull-up

			resistor and the thermistor for GEN4 FG.

- qcom,therm-pull-up: Specifies the thermistor pull-up resistor value in

			KOhms.

- qcom,rslow-normal-coeffs: Array of Rslow coefficients that will be applied

			when the battery temperature is greater than 0 degree

			Celsius for GEN4 FG. This should be exactly of size 4.

drivers/power/supply/qcom/fg-core.h

+1 −0
Original line number Diff line number Diff line
@@ -291,6 +291,7 @@ struct fg_batt_props { 
	int		fastchg_curr_ma;

	int		*therm_coeffs;

	int		therm_ctr_offset;

	int		therm_pull_up_kohms;

	int		*rslow_normal_coeffs;

	int		*rslow_low_coeffs;

};

drivers/power/supply/qcom/fg-reg.h

+6 −0
Original line number Diff line number Diff line
@@ -35,6 +35,12 @@ 
#define ADC_RR_BATT_ID_LO_BIAS_LSB(chip)	(chip->rradc_base + 0x76)

#define ADC_RR_BATT_ID_LO_BIAS_MSB(chip)	(chip->rradc_base + 0x77)



#define ADC_RR_BATT_THERM_BASE_CFG1(chip)	(chip->rradc_base + 0x81)

#define BATT_THERM_PULL_UP_30K			1

#define BATT_THERM_PULL_UP_100K			2

#define BATT_THERM_PULL_UP_400K			3

#define BATT_THERM_PULL_UP_MASK			GENMASK(1, 0)



#define ADC_RR_BATT_TEMP_LSB(chip)		(chip->rradc_base + 0x88)

#define ADC_RR_BATT_TEMP_MSB(chip)		(chip->rradc_base + 0x89)

#define GEN4_BATT_TEMP_MSB_MASK			GENMASK(1, 0)

drivers/power/supply/qcom/qpnp-fg-gen4.c

+33 −0
Original line number Diff line number Diff line
@@ -999,6 +999,15 @@ static int fg_gen4_get_batt_profile(struct fg_dev *fg) 
		}

	}



	if (of_find_property(profile_node, "qcom,therm-pull-up", NULL)) {

		rc = of_property_read_u32(profile_node, "qcom,therm-pull-up",

				&fg->bp.therm_pull_up_kohms);

		if (rc < 0) {

			pr_err("Couldn't read therm-pull-up, rc:%d\n", rc);

			fg->bp.therm_pull_up_kohms = -EINVAL;

		}

	}



	if (of_find_property(profile_node, "qcom,rslow-normal-coeffs", NULL) &&

		of_find_property(profile_node, "qcom,rslow-low-coeffs", NULL)) {

		if (!fg->bp.rslow_normal_coeffs) {
@@ -1121,6 +1130,30 @@ static int fg_gen4_bp_params_config(struct fg_dev *fg) 
		fg_dbg(fg, FG_STATUS, "Rslow_low: %d\n", chip->rslow_low);

	}



	if (fg->bp.therm_pull_up_kohms > 0) {

		switch (fg->bp.therm_pull_up_kohms) {

		case 30:

			buf = BATT_THERM_PULL_UP_30K;

			break;

		case 100:

			buf = BATT_THERM_PULL_UP_100K;

			break;

		case 400:

			buf = BATT_THERM_PULL_UP_400K;

			break;

		default:

			return -EINVAL;

		}



		rc = fg_masked_write(fg, ADC_RR_BATT_THERM_BASE_CFG1(fg),

					BATT_THERM_PULL_UP_MASK, buf);

		if (rc < 0) {

			pr_err("failed to write to 0x%04X, rc=%d\n",

				ADC_RR_BATT_THERM_BASE_CFG1(fg), rc);

			return rc;

		}

	}



	return 0;

}