irqchip/mxs: Add Alphascale ASM9260 support

	select IRQ_DOMAIN

	help

	  Enables the wakeup IRQs for IMX platforms with GPCv2 block

config IRQ_MXS

	def_bool y if MACH_ASM9260 || ARCH_MXS

	select IRQ_DOMAIN

	select STMP_DEVICE

obj-$(CONFIG_ARCH_HIP04)		+= irq-hip04.o

obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o

obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o

obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o

obj-$(CONFIG_IRQ_MXS)			+= irq-mxs.o

obj-$(CONFIG_ARCH_TEGRA)		+= irq-tegra.o

obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o

obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o

/*

 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */

#ifndef _ALPHASCALE_ASM9260_ICOLL_H

#define _ALPHASCALE_ASM9260_ICOLL_H

#define ASM9260_NUM_IRQS		64

/*

 * this device provide 4 offsets for each register:

 * 0x0 - plain read write mode

 * 0x4 - set mode, OR logic.

 * 0x8 - clr mode, XOR logic.

 * 0xc - togle mode.

 */

#define ASM9260_HW_ICOLL_VECTOR				0x0000

/*

 * bits 31:2

 * This register presents the vector address for the interrupt currently

 * active on the CPU IRQ input. Writing to this register notifies the

 * interrupt collector that the interrupt service routine for the current

 * interrupt has been entered.

 * The exception trap should have a LDPC instruction from this address:

 * LDPC ASM9260_HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018

 */

/*

 * The Interrupt Collector Level Acknowledge Register is used by software to

 * indicate the completion of an interrupt on a specific level.

 * This register is written at the very end of an interrupt service routine. If

 * nesting is used then the CPU irq must be turned on before writing to this

 * register to avoid a race condition in the CPU interrupt hardware.

 */

#define ASM9260_HW_ICOLL_LEVELACK			0x0010

#define ASM9260_BM_LEVELn(nr)				BIT(nr)

#define ASM9260_HW_ICOLL_CTRL				0x0020

/*

 * ASM9260_BM_CTRL_SFTRST and ASM9260_BM_CTRL_CLKGATE are not available on

 * asm9260.

 */

#define ASM9260_BM_CTRL_SFTRST				BIT(31)

#define ASM9260_BM_CTRL_CLKGATE				BIT(30)

/* disable interrupt level nesting */

#define ASM9260_BM_CTRL_NO_NESTING			BIT(19)

/*

 * Set this bit to one enable the RISC32-style read side effect associated with

 * the vector address register. In this mode, interrupt in-service is signaled

 * by the read of the ASM9260_HW_ICOLL_VECTOR register to acquire the interrupt

 * vector address. Set this bit to zero for normal operation, in which the ISR

 * signals in-service explicitly by means of a write to the

 * ASM9260_HW_ICOLL_VECTOR register.

 * 0 - Must Write to Vector register to go in-service.

 * 1 - Go in-service as a read side effect

 */

#define ASM9260_BM_CTRL_ARM_RSE_MODE			BIT(18)

#define ASM9260_BM_CTRL_IRQ_ENABLE			BIT(16)

#define ASM9260_HW_ICOLL_STAT_OFFSET			0x0030

/*

 * bits 5:0

 * Vector number of current interrupt. Multiply by 4 and add to vector base

 * address to obtain the value in ASM9260_HW_ICOLL_VECTOR.

 */

/*

 * RAW0 and RAW1 provides a read-only view of the raw interrupt request lines

 * coming from various parts of the chip. Its purpose is to improve diagnostic

 * observability.

 */

#define ASM9260_HW_ICOLL_RAW0				0x0040

#define ASM9260_HW_ICOLL_RAW1				0x0050

#define ASM9260_HW_ICOLL_INTERRUPT0			0x0060

#define ASM9260_HW_ICOLL_INTERRUPTn(n)		(0x0060 + ((n) >> 2) * 0x10)

/*

 * WARNING: Modifying the priority of an enabled interrupt may result in

 * undefined behavior.

 */

#define ASM9260_BM_INT_PRIORITY_MASK			0x3

#define ASM9260_BM_INT_ENABLE				BIT(2)

#define ASM9260_BM_INT_SOFTIRQ				BIT(3)

#define ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n)		(((n) & 0x3) << 3)

#define ASM9260_BM_ICOLL_INTERRUPTn_ENABLE(n)		(1 << (2 + \

			ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n)))

#define ASM9260_HW_ICOLL_VBASE				0x0160

/*

 * bits 31:2

 * This bitfield holds the upper 30 bits of the base address of the vector

 * table.

 */

#define ASM9260_HW_ICOLL_CLEAR0				0x01d0

#define ASM9260_HW_ICOLL_CLEAR1				0x01e0

#define ASM9260_HW_ICOLL_CLEARn(n)			(((n >> 5) * 0x10) \

							+ SET_REG)

#define ASM9260_BM_CLEAR_BIT(n)				BIT(n & 0x1f)

/* Scratchpad */

#define ASM9260_HW_ICOLL_UNDEF_VECTOR			0x01f0

#endif

/*

 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.

 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>

 *	Add Alphascale ASM9260 support.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

#include <linux/stmp_device.h>

#include <asm/exception.h>

#include "alphascale_asm9260-icoll.h"

/*

 * this device provide 4 offsets for each register:

 * 0x0 - plain read write mode

#define ICOLL_NUM_IRQS		128

enum icoll_type {

	ICOLL,

	ASM9260_ICOLL,

};

struct icoll_priv {

	void __iomem *vector;

	void __iomem *levelack;

	void __iomem *ctrl;

	void __iomem *stat;

	void __iomem *intr;

	void __iomem *clear;

	enum icoll_type type;

};

static struct icoll_priv icoll_priv;

static struct irq_domain *icoll_domain;

/* calculate bit offset depending on number of intterupt per register */

static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)

{

	/*

	 * mask lower part of hwirq to convert it

	 * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)

	 */

	return bit << ((d->hwirq & 3) << 3);

}

/* calculate mem offset depending on number of intterupt per register */

static void __iomem *icoll_intr_reg(struct irq_data *d)

{

	/* offset = hwirq / intr_per_reg * 0x10 */

	return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);

}

static void icoll_ack_irq(struct irq_data *d)

{

	/*

			icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));

}

static void asm9260_mask_irq(struct irq_data *d)

{

	__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),

			icoll_intr_reg(d) + CLR_REG);

}

static void asm9260_unmask_irq(struct irq_data *d)

{

	__raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),

		     icoll_priv.clear +

		     ASM9260_HW_ICOLL_CLEARn(d->hwirq));

	__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),

			icoll_intr_reg(d) + SET_REG);

}

static struct irq_chip mxs_icoll_chip = {

	.irq_ack = icoll_ack_irq,

	.irq_mask = icoll_mask_irq,

	.irq_unmask = icoll_unmask_irq,

};

static struct irq_chip asm9260_icoll_chip = {

	.irq_ack = icoll_ack_irq,

	.irq_mask = asm9260_mask_irq,

	.irq_unmask = asm9260_unmask_irq,

};

asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)

{

	u32 irqnr;

static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,

				irq_hw_number_t hw)

{

	irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);

	struct irq_chip *chip;

	if (icoll_priv.type == ICOLL)

		chip = &mxs_icoll_chip;

	else

		chip = &asm9260_icoll_chip;

	irq_set_chip_and_handler(virq, chip, handle_level_irq);

	return 0;

}

{

	void __iomem *icoll_base;

	icoll_priv.type = ICOLL;

	icoll_base		= icoll_init_iobase(np);

	icoll_priv.vector	= icoll_base + HW_ICOLL_VECTOR;

	icoll_priv.levelack	= icoll_base + HW_ICOLL_LEVELACK;

	icoll_priv.ctrl		= icoll_base + HW_ICOLL_CTRL;

	icoll_priv.stat		= icoll_base + HW_ICOLL_STAT_OFFSET;

	icoll_priv.intr		= icoll_base + HW_ICOLL_INTERRUPT0;

	icoll_priv.clear	= NULL;

	/*

	 * Interrupt Collector reset, which initializes the priority

	return 0;

}

IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);

static int __init asm9260_of_init(struct device_node *np,

			  struct device_node *interrupt_parent)

{

	void __iomem *icoll_base;

	int i;

	icoll_priv.type = ASM9260_ICOLL;

	icoll_base = icoll_init_iobase(np);

	icoll_priv.vector	= icoll_base + ASM9260_HW_ICOLL_VECTOR;

	icoll_priv.levelack	= icoll_base + ASM9260_HW_ICOLL_LEVELACK;

	icoll_priv.ctrl		= icoll_base + ASM9260_HW_ICOLL_CTRL;

	icoll_priv.stat		= icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;

	icoll_priv.intr		= icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;

	icoll_priv.clear	= icoll_base + ASM9260_HW_ICOLL_CLEAR0;

	writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,

			icoll_priv.ctrl);

	/*

	 * ASM9260 don't provide reset bit. So, we need to set level 0

	 * manually.

	 */

	for (i = 0; i < 16 * 0x10; i += 0x10)

		writel(0, icoll_priv.intr + i);

	icoll_add_domain(np, ASM9260_NUM_IRQS);

	return 0;

}

IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);