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Commit 7e1c6db3 authored by Abhijit Kulkarni's avatar Abhijit Kulkarni Committed by Ashwini Muduganti
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drm/msm/sde: add api to set clk_rate for a particular clock 



This change adds support to set_rate on a single clock instead
of all the clocks in the module. This is required when CRTC
votes for the core clock, other clock rate change should not be
triggered. This change is required since rot_clk rate should
be set only once during bootup from the drm driver.
Rotator driver calculates the rate for rot_clk based on the session
parameters and drm driver should not touch it for any frame update.

Change-Id: Iaf27ed6e425b369c3f166f8f131440abd484e071
Signed-off-by: default avatarAbhijit Kulkarni <kabhijit@codeaurora.org>
parent 4f450422

drivers/gpu/drm/msm/sde_io_util.c

+29 −15
Original line number Diff line number Diff line
@@ -389,27 +389,41 @@ int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk) 
} /* msm_dss_get_clk */

EXPORT_SYMBOL(msm_dss_get_clk);



int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk)

int msm_dss_single_clk_set_rate(struct dss_clk *clk)

{

	int i, rc = 0;

	int rc = 0;



	for (i = 0; i < num_clk; i++) {

		if (clk_arry[i].clk) {

			if (clk_arry[i].type != DSS_CLK_AHB) {

				DEV_DBG("%pS->%s: '%s' rate %ld\n",

	if (!clk) {

		DEV_ERR("invalid clk struct\n");

		return -EINVAL;

	}



	DEV_DBG("%pS->%s: set_rate '%s'\n",

			__builtin_return_address(0), __func__,

					clk_arry[i].clk_name,

					clk_arry[i].rate);

				rc = clk_set_rate(clk_arry[i].clk,

					clk_arry[i].rate);

				if (rc) {

			clk->clk_name);



	if (clk->type != DSS_CLK_AHB) {

		rc = clk_set_rate(clk->clk, clk->rate);

		if (rc)

			DEV_ERR("%pS->%s: %s failed. rc=%d\n",

					__builtin_return_address(0),

					__func__,

						clk_arry[i].clk_name, rc);

					break;

				}

					clk->clk_name, rc);

	}



	return rc;

} /* msm_dss_single_clk_set_rate */

EXPORT_SYMBOL(msm_dss_single_clk_set_rate);



int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk)

{

	int i, rc = 0;



	for (i = 0; i < num_clk; i++) {

		if (clk_arry[i].clk) {

			rc = msm_dss_single_clk_set_rate(&clk_arry[i]);

			if (rc)

				break;

		} else {

			DEV_ERR("%pS->%s: '%s' is not available\n",

				__builtin_return_address(0), __func__,

drivers/gpu/drm/msm/sde_power_handle.c

+1 −1
Original line number Diff line number Diff line
@@ -1137,7 +1137,7 @@ int sde_power_clk_set_rate(struct sde_power_handle *phandle, char *clock_name, 
			sde_cx_ipeak_vote(phandle, &mp->clk_config[i],

				requested_clk_rate, prev_clk_rate, true);

			mp->clk_config[i].rate = rate;

			rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);

			rc = msm_dss_single_clk_set_rate(&mp->clk_config[i]);

			if (!rc)

				sde_cx_ipeak_vote(phandle, &mp->clk_config[i],

				   requested_clk_rate, prev_clk_rate, false);

include/linux/sde_io_util.h

+2 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -103,6 +103,7 @@ int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable); 
int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);

void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);

int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);

int msm_dss_single_clk_set_rate(struct dss_clk *clk);

int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);



int sde_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,