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Commit 7d9b5ba9 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add measure support ddr clock for SM6150"

parents c5ef9718 ab2b4086

arch/arm64/boot/dts/qcom/sm6150.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -815,6 +815,11 @@ 
		reg = <0x182a0018 0x4>;

	};



	mccc_debug: syscon@90b0000 {

		compatible = "syscon";

		reg = <0x90b0000 0x1000>;

	};



	clock_cpucc: qcom,cpucc@18321000 {

		compatible = "qcom,clk-cpu-osm-sm6150";

		reg = <0x18321000 0x1400>,
@@ -835,6 +840,7 @@ 
		qcom,dispcc = <&clock_dispcc>;

		qcom,gpucc = <&clock_gpucc>;

		qcom,cpucc = <&cpucc_debug>;

		qcom,mccc = <&mccc_debug>;

		clock-names = "cxo";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		#clock-cells = <1>;

drivers/clk/qcom/debugcc-sm6150.c

+8 −3
Original line number Diff line number Diff line
@@ -240,7 +240,7 @@ static const char *const debug_mux_parent_names[] = { 
	"gpu_cc_gx_qdss_tsctr_clk",

	"gpu_cc_gx_vsense_clk",

	"gpu_cc_sleep_clk",

	"measure_only_bimc_clk",

	"measure_only_mccc_clk",

	"measure_only_cnoc_clk",

	"measure_only_ipa_2x_clk",

	"measure_only_snoc_clk",
@@ -269,6 +269,7 @@ static struct clk_debug_mux gcc_debug_mux = { 
	.src_sel_shift = 0,

	.post_div_mask = 0xF,

	.post_div_shift = 0,

	.period_offset = 0x50,

	MUX_SRC_LIST(

		{ "cam_cc_bps_ahb_clk", 0x46, 1, CAM_CC,

			0xE, 0xFF, 0, 0x3, 0, 2, 0xC000, 0xC004, 0xC008 },
@@ -684,8 +685,8 @@ static struct clk_debug_mux gcc_debug_mux = { 
			0xC, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "gpu_cc_sleep_clk", 0x144, 1, GPU_CC,

			0x16, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 },

		{ "measure_only_bimc_clk", 0xC2, 1, GCC,

			0xBF, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "measure_only_mccc_clk", 0xC2, 1, MC_CC,

			0xC2, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "measure_only_cnoc_clk", 0x15, 1, GCC,

			0x15, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },

		{ "measure_only_ipa_2x_clk", 0x128, 1, GCC,
@@ -797,6 +798,10 @@ static int clk_debug_sm6150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	ret = map_debug_bases(pdev, "qcom,mccc", MC_CC);

	if (ret)

		return ret;



	clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);

	if (IS_ERR(clk)) {

		dev_err(&pdev->dev, "Unable to register GCC debug mux\n");

drivers/clk/qcom/gcc-sm6150.c

+3 −3
Original line number Diff line number Diff line
@@ -3191,10 +3191,10 @@ static struct clk_branch gcc_usb2_sec_clkref_clk = { 
};



/* Measure-only clock for ddrss_gcc_debug_clk. */

static struct clk_dummy measure_only_bimc_clk = {

static struct clk_dummy measure_only_mccc_clk = {

	.rrate = 1000,

	.hw.init = &(struct clk_init_data){

		.name = "measure_only_bimc_clk",

		.name = "measure_only_mccc_clk",

		.ops = &clk_dummy_ops,

	},

};
@@ -3228,7 +3228,7 @@ static struct clk_dummy measure_only_snoc_clk = { 


struct clk_hw *gcc_sm6150_hws[] = {

	[GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw,

	[MEASURE_ONLY_BIMC_CLK] = &measure_only_bimc_clk.hw,

	[MEASURE_ONLY_MMCC_CLK] = &measure_only_mccc_clk.hw,

	[MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw,

	[MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw,

	[MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw,

include/dt-bindings/clock/qcom,gcc-sm6150.h

+1 −1
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
#define GPLL0_OUT_AUX2				0

#define MEASURE_ONLY_SNOC_CLK			1

#define MEASURE_ONLY_CNOC_CLK			2

#define MEASURE_ONLY_BIMC_CLK			3

#define MEASURE_ONLY_MMCC_CLK			3

#define MEASURE_ONLY_IPA_2X_CLK			4



/* GCC clock registers */