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Commit 7d42028b authored by Tingwei Zhang's avatar Tingwei Zhang
Browse files

coresight: byte-cntr: Read 64bit rwp 



TMC RWP has two 32bit registers which combine to one 64bit register.
Read correct RWP register in byte counter driver.

Change-Id: If4a204110e0cc97d65e8a6af37ca764ffb38a150
Signed-off-by: default avatarTingwei Zhang <tingwei@codeaurora.org>
parent 06b9fb52

drivers/hwtracing/coresight/coresight-byte-cntr.c

+3 −2
Original line number Diff line number Diff line
@@ -47,7 +47,8 @@ static void tmc_etr_sg_read_pos(loff_t *ppos, 
				size_t bytes, bool noirq, size_t *len,

				char **bufpp)

{

	uint32_t rwp, i = 0;

	uint32_t i = 0;

	u64 rwp;

	uint32_t blk_num, sg_tbl_num, blk_num_loc, read_off;

	uint32_t *virt_pte, *virt_st_tbl;

	void *virt_blk;
@@ -86,7 +87,7 @@ static void tmc_etr_sg_read_pos(loff_t *ppos, 
	*bufpp = (char *)(virt_blk + read_off);



	if (noirq) {

		rwp = readl_relaxed(tmcdrvdata->base + TMC_RWP);

		rwp = tmc_read_rwp(tmcdrvdata);

		tmc_etr_sg_rwp_pos(tmcdrvdata, rwp);

		if (tmcdrvdata->sg_blk_num == blk_num &&

		    rwp >= (phys_pte + read_off))