Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7c859007 authored by Zhe Wang's avatar Zhe Wang Committed by Daniel Vetter
Browse files

drm/i915: Gen9 shadowed registers 



For MMIO registers which are shadowed, force wake is not needed to
write to these registers.

v2: Rebase on top of nightly (Damien)

v3: Rebase on top of "Gen9 multiple-engine forcewake" changes

v4: (Mika, Bob, done by Damien)
- Reorder the shadowed registers by popularity

Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarZhe Wang <zhe1.wang@intel.com>
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4597a88a

drivers/gpu/drm/i915/intel_uncore.c

+25 −1
Original line number Diff line number Diff line
@@ -1026,12 +1026,36 @@ chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) 
	REG_WRITE_FOOTER; \

}



static const u32 gen9_shadowed_regs[] = {

	RING_TAIL(RENDER_RING_BASE),

	RING_TAIL(GEN6_BSD_RING_BASE),

	RING_TAIL(VEBOX_RING_BASE),

	RING_TAIL(BLT_RING_BASE),

	FORCEWAKE_BLITTER_GEN9,

	FORCEWAKE_RENDER_GEN9,

	FORCEWAKE_MEDIA_GEN9,

	GEN6_RPNSWREQ,

	GEN6_RC_VIDEO_FREQ,

	/* TODO: Other registers are not yet used */

};



static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)

{

	int i;

	for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)

		if (reg == gen9_shadowed_regs[i])

			return true;



	return false;

}



#define __gen9_write(x) \

static void \

gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \

		bool trace) { \

	REG_WRITE_HEADER; \

	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

	if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \

			is_gen9_shadowed(dev_priv, reg)) { \

		__raw_i915_write##x(dev_priv, reg, val); \

	} else { \

		unsigned fwengine = 0; \