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Commit 7c11c99b authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/bios/dcb: accept "maxwell" lane count values for dcb 4.0 



We previously assumed that the values "2" and "4" were new in DCB 4.1,
however, there's at least one GM107 DCB 4.0 board (Quadro K620) that
uses the newer values.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 895fb8e6

drivers/gpu/drm/nouveau/nouveau_bios.c

+12 −13
Original line number Diff line number Diff line
@@ -1481,20 +1481,19 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 
			entry->dpconf.link_bw = 540000;

			break;

		}

		entry->dpconf.link_nr = (conf & 0x0f000000) >> 24;

		if (dcb->version < 0x41) {

			switch (entry->dpconf.link_nr) {

		switch ((conf & 0x0f000000) >> 24) {

		case 0xf:

		case 0x4:

			entry->dpconf.link_nr = 4;

			break;

		case 0x3:

		case 0x2:

			entry->dpconf.link_nr = 2;

			break;

		default:

			entry->dpconf.link_nr = 1;

			break;

		}

		}

		link = entry->dpconf.sor.link;

		entry->i2c_index += NV_I2C_AUX(0);

		break;

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c

+13 −14
Original line number Diff line number Diff line
@@ -156,21 +156,20 @@ dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, 
					break;

				}



				outp->dpconf.link_nr = (conf & 0x0f000000) >> 24;

				if (*ver < 0x41) {

					switch (outp->dpconf.link_nr) {

					case 0x0f:

				switch ((conf & 0x0f000000) >> 24) {

				case 0xf:

				case 0x4:

					outp->dpconf.link_nr = 4;

					break;

					case 0x03:

				case 0x3:

				case 0x2:

					outp->dpconf.link_nr = 2;

					break;

					case 0x01:

				case 0x1:

				default:

					outp->dpconf.link_nr = 1;

					break;

				}

				}



				/* fall-through... */

			case DCB_OUTPUT_TMDS: