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Commit 7c10a2b5 authored by Jani Nikula's avatar Jani Nikula Committed by Daniel Vetter
Browse files

drm/i915: add new intel audio file to group DP/HDMI audio 



In preparation for some additional cleanup. No functional changes.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3ead8bb2

drivers/gpu/drm/i915/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -44,7 +44,8 @@ i915-y += intel_renderstate_gen6.o \ 
	  intel_renderstate_gen9.o



# modesetting core code

i915-y += intel_bios.o \

i915-y += intel_audio.o \

	  intel_bios.o \

	  intel_display.o \

	  intel_fifo_underrun.o \

	  intel_frontbuffer.o \

drivers/gpu/drm/i915/intel_audio.c

0 → 100644
+357 −0
Original line number Diff line number Diff line 
/*

 * Copyright © 2014 Intel Corporation

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



#include <linux/kernel.h>



#include <drm/drmP.h>

#include <drm/drm_edid.h>

#include "intel_drv.h"

#include "i915_drv.h"



static struct {

	int clock;

	u32 config;

} hdmi_audio_clock[] = {

	{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },

	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */

	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },

	{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },

	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },

	{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },

	{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },

	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },

	{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },

	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },

};



/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */

static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {

		if (mode->clock == hdmi_audio_clock[i].clock)

			break;

	}



	if (i == ARRAY_SIZE(hdmi_audio_clock)) {

		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);

		i = 1;

	}



	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",

		      hdmi_audio_clock[i].clock,

		      hdmi_audio_clock[i].config);



	return hdmi_audio_clock[i].config;

}



static bool intel_eld_uptodate(struct drm_connector *connector,

			       int reg_eldv, uint32_t bits_eldv,

			       int reg_elda, uint32_t bits_elda,

			       int reg_edid)

{

	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	uint8_t *eld = connector->eld;

	uint32_t i;



	i = I915_READ(reg_eldv);

	i &= bits_eldv;



	if (!eld[0])

		return !i;



	if (!i)

		return false;



	i = I915_READ(reg_elda);

	i &= ~bits_elda;

	I915_WRITE(reg_elda, i);



	for (i = 0; i < eld[2]; i++)

		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))

			return false;



	return true;

}



static void g4x_write_eld(struct drm_connector *connector,

			  struct drm_crtc *crtc,

			  struct drm_display_mode *mode)

{

	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	uint8_t *eld = connector->eld;

	uint32_t eldv;

	uint32_t len;

	uint32_t i;



	i = I915_READ(G4X_AUD_VID_DID);



	if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)

		eldv = G4X_ELDV_DEVCL_DEVBLC;

	else

		eldv = G4X_ELDV_DEVCTG;



	if (intel_eld_uptodate(connector,

			       G4X_AUD_CNTL_ST, eldv,

			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR,

			       G4X_HDMIW_HDMIEDID))

		return;



	i = I915_READ(G4X_AUD_CNTL_ST);

	i &= ~(eldv | G4X_ELD_ADDR);

	len = (i >> 9) & 0x1f;		/* ELD buffer size */

	I915_WRITE(G4X_AUD_CNTL_ST, i);



	if (!eld[0])

		return;



	len = min_t(uint8_t, eld[2], len);

	DRM_DEBUG_DRIVER("ELD size %d\n", len);

	for (i = 0; i < len; i++)

		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));



	i = I915_READ(G4X_AUD_CNTL_ST);

	i |= eldv;

	I915_WRITE(G4X_AUD_CNTL_ST, i);

}



static void haswell_write_eld(struct drm_connector *connector,

			      struct drm_crtc *crtc,

			      struct drm_display_mode *mode)

{

	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	uint8_t *eld = connector->eld;

	uint32_t eldv;

	uint32_t i;

	int len;

	int pipe = to_intel_crtc(crtc)->pipe;

	int tmp;



	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);

	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);

	int aud_config = HSW_AUD_CFG(pipe);

	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;



	/* Audio output enable */

	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");

	tmp = I915_READ(aud_cntrl_st2);

	tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));

	I915_WRITE(aud_cntrl_st2, tmp);

	POSTING_READ(aud_cntrl_st2);



	assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);



	/* Set ELD valid state */

	tmp = I915_READ(aud_cntrl_st2);

	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);

	tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));

	I915_WRITE(aud_cntrl_st2, tmp);

	tmp = I915_READ(aud_cntrl_st2);

	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);



	/* Enable HDMI mode */

	tmp = I915_READ(aud_config);

	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);

	/* clear N_programing_enable and N_value_index */

	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);

	I915_WRITE(aud_config, tmp);



	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));



	eldv = AUDIO_ELD_VALID_A << (pipe * 4);



	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {

		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");

		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */

		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */

	} else {

		I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));

	}



	if (intel_eld_uptodate(connector,

			       aud_cntrl_st2, eldv,

			       aud_cntl_st, IBX_ELD_ADDRESS,

			       hdmiw_hdmiedid))

		return;



	i = I915_READ(aud_cntrl_st2);

	i &= ~eldv;

	I915_WRITE(aud_cntrl_st2, i);



	if (!eld[0])

		return;



	i = I915_READ(aud_cntl_st);

	i &= ~IBX_ELD_ADDRESS;

	I915_WRITE(aud_cntl_st, i);

	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */

	DRM_DEBUG_DRIVER("port num:%d\n", i);



	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */

	DRM_DEBUG_DRIVER("ELD size %d\n", len);

	for (i = 0; i < len; i++)

		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));



	i = I915_READ(aud_cntrl_st2);

	i |= eldv;

	I915_WRITE(aud_cntrl_st2, i);



}



static void ironlake_write_eld(struct drm_connector *connector,

			       struct drm_crtc *crtc,

			       struct drm_display_mode *mode)

{

	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	uint8_t *eld = connector->eld;

	uint32_t eldv;

	uint32_t i;

	int len;

	int hdmiw_hdmiedid;

	int aud_config;

	int aud_cntl_st;

	int aud_cntrl_st2;

	int pipe = to_intel_crtc(crtc)->pipe;



	if (HAS_PCH_IBX(connector->dev)) {

		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);

		aud_config = IBX_AUD_CFG(pipe);

		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);

		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;

	} else if (IS_VALLEYVIEW(connector->dev)) {

		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);

		aud_config = VLV_AUD_CFG(pipe);

		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);

		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;

	} else {

		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);

		aud_config = CPT_AUD_CFG(pipe);

		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);

		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;

	}



	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));



	if (IS_VALLEYVIEW(connector->dev))  {

		struct intel_encoder *intel_encoder;

		struct intel_digital_port *intel_dig_port;



		intel_encoder = intel_attached_encoder(connector);

		intel_dig_port = enc_to_dig_port(&intel_encoder->base);

		i = intel_dig_port->port;

	} else {

		i = I915_READ(aud_cntl_st);

		i = (i >> 29) & DIP_PORT_SEL_MASK;

		/* DIP_Port_Select, 0x1 = PortB */

	}



	if (!i) {

		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");

		/* operate blindly on all ports */

		eldv = IBX_ELD_VALIDB;

		eldv |= IBX_ELD_VALIDB << 4;

		eldv |= IBX_ELD_VALIDB << 8;

	} else {

		DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));

		eldv = IBX_ELD_VALIDB << ((i - 1) * 4);

	}



	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {

		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");

		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */

		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */

	} else {

		I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));

	}



	if (intel_eld_uptodate(connector,

			       aud_cntrl_st2, eldv,

			       aud_cntl_st, IBX_ELD_ADDRESS,

			       hdmiw_hdmiedid))

		return;



	i = I915_READ(aud_cntrl_st2);

	i &= ~eldv;

	I915_WRITE(aud_cntrl_st2, i);



	if (!eld[0])

		return;



	i = I915_READ(aud_cntl_st);

	i &= ~IBX_ELD_ADDRESS;

	I915_WRITE(aud_cntl_st, i);



	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */

	DRM_DEBUG_DRIVER("ELD size %d\n", len);

	for (i = 0; i < len; i++)

		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));



	i = I915_READ(aud_cntrl_st2);

	i |= eldv;

	I915_WRITE(aud_cntrl_st2, i);

}



void intel_write_eld(struct drm_encoder *encoder,

		     struct drm_display_mode *mode)

{

	struct drm_crtc *crtc = encoder->crtc;

	struct drm_connector *connector;

	struct drm_device *dev = encoder->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	connector = drm_select_eld(encoder, mode);

	if (!connector)

		return;



	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

			 connector->base.id,

			 connector->name,

			 connector->encoder->base.id,

			 connector->encoder->name);



	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;



	if (dev_priv->display.write_eld)

		dev_priv->display.write_eld(connector, crtc, mode);

}



/**

 * intel_init_audio - Set up chip specific audio functions

 * @dev: drm device

 */

void intel_init_audio(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (IS_G4X(dev))

		dev_priv->display.write_eld = g4x_write_eld;

	else if (IS_VALLEYVIEW(dev))

		dev_priv->display.write_eld = ironlake_write_eld;

	else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)

		dev_priv->display.write_eld = haswell_write_eld;

	else if (HAS_PCH_SPLIT(dev))

		dev_priv->display.write_eld = ironlake_write_eld;

}

drivers/gpu/drm/i915/intel_display.c

+3 −320
Original line number Diff line number Diff line
@@ -406,7 +406,7 @@ static void vlv_clock(int refclk, intel_clock_t *clock) 
/**

 * Returns whether any output on the specified pipe is of the specified type

 */

static bool intel_pipe_has_type(struct intel_crtc *crtc, int type)

bool intel_pipe_has_type(struct intel_crtc *crtc, int type)

{

	struct drm_device *dev = crtc->base.dev;

	struct intel_encoder *encoder;
@@ -7940,316 +7940,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, 
	return true;

}



static struct {

	int clock;

	u32 config;

} hdmi_audio_clock[] = {

	{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },

	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */

	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },

	{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },

	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },

	{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },

	{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },

	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },

	{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },

	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },

};



/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */

static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {

		if (mode->clock == hdmi_audio_clock[i].clock)

			break;

	}



	if (i == ARRAY_SIZE(hdmi_audio_clock)) {

		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);

		i = 1;

	}



	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",

		      hdmi_audio_clock[i].clock,

		      hdmi_audio_clock[i].config);



	return hdmi_audio_clock[i].config;

}



static bool intel_eld_uptodate(struct drm_connector *connector,

			       int reg_eldv, uint32_t bits_eldv,

			       int reg_elda, uint32_t bits_elda,

			       int reg_edid)

{

	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	uint8_t *eld = connector->eld;

	uint32_t i;



	i = I915_READ(reg_eldv);

	i &= bits_eldv;



	if (!eld[0])

		return !i;



	if (!i)

		return false;



	i = I915_READ(reg_elda);

	i &= ~bits_elda;

	I915_WRITE(reg_elda, i);



	for (i = 0; i < eld[2]; i++)

		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))

			return false;



	return true;

}



static void g4x_write_eld(struct drm_connector *connector,

			  struct drm_crtc *crtc,

			  struct drm_display_mode *mode)

{

	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	uint8_t *eld = connector->eld;

	uint32_t eldv;

	uint32_t len;

	uint32_t i;



	i = I915_READ(G4X_AUD_VID_DID);



	if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)

		eldv = G4X_ELDV_DEVCL_DEVBLC;

	else

		eldv = G4X_ELDV_DEVCTG;



	if (intel_eld_uptodate(connector,

			       G4X_AUD_CNTL_ST, eldv,

			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR,

			       G4X_HDMIW_HDMIEDID))

		return;



	i = I915_READ(G4X_AUD_CNTL_ST);

	i &= ~(eldv | G4X_ELD_ADDR);

	len = (i >> 9) & 0x1f;		/* ELD buffer size */

	I915_WRITE(G4X_AUD_CNTL_ST, i);



	if (!eld[0])

		return;



	len = min_t(uint8_t, eld[2], len);

	DRM_DEBUG_DRIVER("ELD size %d\n", len);

	for (i = 0; i < len; i++)

		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));



	i = I915_READ(G4X_AUD_CNTL_ST);

	i |= eldv;

	I915_WRITE(G4X_AUD_CNTL_ST, i);

}



static void haswell_write_eld(struct drm_connector *connector,

			      struct drm_crtc *crtc,

			      struct drm_display_mode *mode)

{

	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	uint8_t *eld = connector->eld;

	uint32_t eldv;

	uint32_t i;

	int len;

	int pipe = to_intel_crtc(crtc)->pipe;

	int tmp;



	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);

	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);

	int aud_config = HSW_AUD_CFG(pipe);

	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;



	/* Audio output enable */

	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");

	tmp = I915_READ(aud_cntrl_st2);

	tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));

	I915_WRITE(aud_cntrl_st2, tmp);

	POSTING_READ(aud_cntrl_st2);



	assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);



	/* Set ELD valid state */

	tmp = I915_READ(aud_cntrl_st2);

	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);

	tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));

	I915_WRITE(aud_cntrl_st2, tmp);

	tmp = I915_READ(aud_cntrl_st2);

	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);



	/* Enable HDMI mode */

	tmp = I915_READ(aud_config);

	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);

	/* clear N_programing_enable and N_value_index */

	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);

	I915_WRITE(aud_config, tmp);



	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));



	eldv = AUDIO_ELD_VALID_A << (pipe * 4);



	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {

		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");

		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */

		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */

	} else {

		I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));

	}



	if (intel_eld_uptodate(connector,

			       aud_cntrl_st2, eldv,

			       aud_cntl_st, IBX_ELD_ADDRESS,

			       hdmiw_hdmiedid))

		return;



	i = I915_READ(aud_cntrl_st2);

	i &= ~eldv;

	I915_WRITE(aud_cntrl_st2, i);



	if (!eld[0])

		return;



	i = I915_READ(aud_cntl_st);

	i &= ~IBX_ELD_ADDRESS;

	I915_WRITE(aud_cntl_st, i);

	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */

	DRM_DEBUG_DRIVER("port num:%d\n", i);



	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */

	DRM_DEBUG_DRIVER("ELD size %d\n", len);

	for (i = 0; i < len; i++)

		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));



	i = I915_READ(aud_cntrl_st2);

	i |= eldv;

	I915_WRITE(aud_cntrl_st2, i);



}



static void ironlake_write_eld(struct drm_connector *connector,

			       struct drm_crtc *crtc,

			       struct drm_display_mode *mode)

{

	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	uint8_t *eld = connector->eld;

	uint32_t eldv;

	uint32_t i;

	int len;

	int hdmiw_hdmiedid;

	int aud_config;

	int aud_cntl_st;

	int aud_cntrl_st2;

	int pipe = to_intel_crtc(crtc)->pipe;



	if (HAS_PCH_IBX(connector->dev)) {

		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);

		aud_config = IBX_AUD_CFG(pipe);

		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);

		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;

	} else if (IS_VALLEYVIEW(connector->dev)) {

		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);

		aud_config = VLV_AUD_CFG(pipe);

		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);

		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;

	} else {

		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);

		aud_config = CPT_AUD_CFG(pipe);

		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);

		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;

	}



	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));



	if (IS_VALLEYVIEW(connector->dev))  {

		struct intel_encoder *intel_encoder;

		struct intel_digital_port *intel_dig_port;



		intel_encoder = intel_attached_encoder(connector);

		intel_dig_port = enc_to_dig_port(&intel_encoder->base);

		i = intel_dig_port->port;

	} else {

		i = I915_READ(aud_cntl_st);

		i = (i >> 29) & DIP_PORT_SEL_MASK;

		/* DIP_Port_Select, 0x1 = PortB */

	}



	if (!i) {

		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");

		/* operate blindly on all ports */

		eldv = IBX_ELD_VALIDB;

		eldv |= IBX_ELD_VALIDB << 4;

		eldv |= IBX_ELD_VALIDB << 8;

	} else {

		DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));

		eldv = IBX_ELD_VALIDB << ((i - 1) * 4);

	}



	if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {

		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");

		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */

		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */

	} else {

		I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));

	}



	if (intel_eld_uptodate(connector,

			       aud_cntrl_st2, eldv,

			       aud_cntl_st, IBX_ELD_ADDRESS,

			       hdmiw_hdmiedid))

		return;



	i = I915_READ(aud_cntrl_st2);

	i &= ~eldv;

	I915_WRITE(aud_cntrl_st2, i);



	if (!eld[0])

		return;



	i = I915_READ(aud_cntl_st);

	i &= ~IBX_ELD_ADDRESS;

	I915_WRITE(aud_cntl_st, i);



	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */

	DRM_DEBUG_DRIVER("ELD size %d\n", len);

	for (i = 0; i < len; i++)

		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));



	i = I915_READ(aud_cntrl_st2);

	i |= eldv;

	I915_WRITE(aud_cntrl_st2, i);

}



void intel_write_eld(struct drm_encoder *encoder,

		     struct drm_display_mode *mode)

{

	struct drm_crtc *crtc = encoder->crtc;

	struct drm_connector *connector;

	struct drm_device *dev = encoder->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	connector = drm_select_eld(encoder, mode);

	if (!connector)

		return;



	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

			 connector->base.id,

			 connector->name,

			 connector->encoder->base.id,

			 connector->encoder->name);



	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;



	if (dev_priv->display.write_eld)

		dev_priv->display.write_eld(connector, crtc, mode);

}



static void i845_update_cursor(struct drm_crtc *crtc, u32 base)

{

	struct drm_device *dev = crtc->dev;
@@ -12638,33 +12328,25 @@ static void intel_init_display(struct drm_device *dev) 
		dev_priv->display.get_display_clock_speed =

			i830_get_display_clock_speed;



	if (IS_G4X(dev)) {

		dev_priv->display.write_eld = g4x_write_eld;

	} else if (IS_GEN5(dev)) {

	if (IS_GEN5(dev)) {

		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;

		dev_priv->display.write_eld = ironlake_write_eld;

	} else if (IS_GEN6(dev)) {

		dev_priv->display.fdi_link_train = gen6_fdi_link_train;

		dev_priv->display.write_eld = ironlake_write_eld;

		dev_priv->display.modeset_global_resources =

			snb_modeset_global_resources;

	} else if (IS_IVYBRIDGE(dev)) {

		/* FIXME: detect B0+ stepping and use auto training */

		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;

		dev_priv->display.write_eld = ironlake_write_eld;

		dev_priv->display.modeset_global_resources =

			ivb_modeset_global_resources;

	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {

		dev_priv->display.fdi_link_train = hsw_fdi_link_train;

		dev_priv->display.write_eld = haswell_write_eld;

		dev_priv->display.modeset_global_resources =

			haswell_modeset_global_resources;

	} else if (IS_VALLEYVIEW(dev)) {

		dev_priv->display.modeset_global_resources =

			valleyview_modeset_global_resources;

		dev_priv->display.write_eld = ironlake_write_eld;

	} else if (INTEL_INFO(dev)->gen >= 9) {

		dev_priv->display.write_eld = haswell_write_eld;

		dev_priv->display.modeset_global_resources =

			haswell_modeset_global_resources;

	}
@@ -12919,6 +12601,7 @@ void intel_modeset_init(struct drm_device *dev) 
		return;



	intel_init_display(dev);

	intel_init_audio(dev);



	if (IS_GEN2(dev)) {

		dev->mode_config.max_width = 2048;

drivers/gpu/drm/i915/intel_drv.h

+6 −2
Original line number Diff line number Diff line
@@ -848,6 +848,11 @@ void intel_frontbuffer_flip(struct drm_device *dev, 
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);





/* intel_audio.c */

void intel_init_audio(struct drm_device *dev);

void intel_write_eld(struct drm_encoder *encoder,

		     struct drm_display_mode *mode);



/* intel_display.c */

const char *intel_output_name(int output);

bool intel_has_pending_fb_unpin(struct drm_device *dev);
@@ -873,6 +878,7 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 
				struct drm_file *file_priv);

enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,

					     enum pipe pipe);

bool intel_pipe_has_type(struct intel_crtc *crtc, int type);

static inline void

intel_wait_for_vblank(struct drm_device *dev, int pipe)

{
@@ -924,8 +930,6 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);

#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)

#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)

void intel_write_eld(struct drm_encoder *encoder,

		     struct drm_display_mode *mode);

unsigned long intel_gen4_compute_page_offset(int *x, int *y,

					     unsigned int tiling_mode,

					     unsigned int bpp,