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Commit 7ba45947 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: Add clock asynchronous resets to BCRs"

parents 9c92f437 43e892a7

drivers/clk/qcom/gcc-sdmmagpie.c

+1 −0
Original line number Diff line number Diff line
@@ -3230,6 +3230,7 @@ static const struct qcom_reset_map gcc_sdmmagpie_resets[] = { 
	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },

	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },

	[GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },

	[GCC_VIDEO_AXI_CLK_BCR] = { 0xb01c, 2 },

};



static struct clk_dfs gcc_dfs_clocks[] = {

drivers/clk/qcom/gcc-sm8150.c

+1 −0
Original line number Diff line number Diff line
@@ -4160,6 +4160,7 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = { 
	[GCC_USB30_PRIM_BCR] = { 0xf000 },

	[GCC_USB30_SEC_BCR] = { 0x10000 },

	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },

	[GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },

};

drivers/clk/qcom/videocc-sm8150.c

+6 −0
Original line number Diff line number Diff line
@@ -299,10 +299,16 @@ static const struct regmap_config video_cc_sm8150_regmap_config = { 
	.fast_io	= true,

};



static const struct qcom_reset_map video_cc_sm8150_resets[] = {

	[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },

};



static const struct qcom_cc_desc video_cc_sm8150_desc = {

	.config = &video_cc_sm8150_regmap_config,

	.clks = video_cc_sm8150_clocks,

	.num_clks = ARRAY_SIZE(video_cc_sm8150_clocks),

	.resets = video_cc_sm8150_resets,

	.num_resets = ARRAY_SIZE(video_cc_sm8150_resets),

};



static const struct of_device_id video_cc_sm8150_match_table[] = {

include/dt-bindings/clock/qcom,gcc-sdmmagpie.h

+1 −0
Original line number Diff line number Diff line
@@ -189,5 +189,6 @@ 
#define GCC_USB3_PHY_PRIM_BCR				7

#define GCC_USB3_PHY_SEC_BCR				8

#define GCC_QUSB2PHY_PRIM_BCR				9

#define GCC_VIDEO_AXI_CLK_BCR				10



#endif

include/dt-bindings/clock/qcom,gcc-sm8150.h

+1 −0
Original line number Diff line number Diff line
@@ -247,6 +247,7 @@ 
#define GCC_USB30_PRIM_BCR					26

#define GCC_USB30_SEC_BCR					27

#define GCC_USB_PHY_CFG_AHB2PHY_BCR				28

#define GCC_VIDEO_AXIC_CLK_BCR					29



/* Dummy clocks for rate measurement */

#define MEASURE_ONLY_SNOC_CLK					0