Loading drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c +13 −1 Original line number Diff line number Diff line Loading @@ -503,6 +503,18 @@ static void __cam_isp_ctx_send_sof_timestamp( } static int __cam_isp_ctx_reg_upd_in_epoch_state( struct cam_isp_context *ctx_isp, void *evt_data) { if (ctx_isp->frame_id == 1) CAM_DBG(CAM_ISP, "Reg update for early PCR"); else CAM_WARN(CAM_ISP, "Unexpected reg update in activated substate:%d for frame_id:%lld", ctx_isp->substate_activated, ctx_isp->frame_id); return 0; } static int __cam_isp_ctx_reg_upd_in_activated_state( struct cam_isp_context *ctx_isp, void *evt_data) { Loading Loading @@ -1118,7 +1130,7 @@ static struct cam_isp_ctx_irq_ops .irq_ops = { __cam_isp_ctx_handle_error, __cam_isp_ctx_sof_in_epoch, NULL, __cam_isp_ctx_reg_upd_in_epoch_state, __cam_isp_ctx_notify_sof_in_activated_state, __cam_isp_ctx_notify_eof_in_activated_state, __cam_isp_ctx_buf_done_in_epoch, Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c +12 −2 Original line number Diff line number Diff line Loading @@ -204,6 +204,9 @@ static int cam_vfe_camif_resource_start( { struct cam_vfe_mux_camif_data *rsrc_data; uint32_t val = 0; uint32_t epoch0_irq_mask; uint32_t epoch1_irq_mask; uint32_t computed_epoch_line_cfg; if (!camif_res) { CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); Loading Loading @@ -243,9 +246,16 @@ static int cam_vfe_camif_resource_start( rsrc_data->common_reg->module_ctrl[ CAM_VFE_TOP_VER2_MODULE_STATS]->cgc_ovd); /* epoch config with 20 line */ cam_io_w_mb(rsrc_data->reg_data->epoch_line_cfg, /* epoch config */ epoch0_irq_mask = ((rsrc_data->last_line - rsrc_data->first_line) / 2) + rsrc_data->first_line; epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg & 0xFFFF; computed_epoch_line_cfg = (epoch0_irq_mask << 16) | epoch1_irq_mask; cam_io_w_mb(computed_epoch_line_cfg, rsrc_data->mem_base + rsrc_data->camif_reg->epoch_irq); CAM_DBG(CAM_ISP, "first_line:%u last_line:%u epoch_line_cfg: 0x%x", rsrc_data->first_line, rsrc_data->last_line, computed_epoch_line_cfg); camif_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; Loading drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +0 −7 Original line number Diff line number Diff line Loading @@ -770,13 +770,6 @@ static int cam_jpeg_mgr_flush(void *hw_mgr_priv, } else { CAM_ERR(CAM_JPEG, "process_cmd null "); } rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd( hw_mgr->devices[dev_type][0]->hw_priv, CAM_JPEG_CMD_SET_IRQ_CB, &irq_cb, sizeof(irq_cb)); if (rc) CAM_ERR(CAM_JPEG, "CMD_SET_IRQ_CB failed %d", rc); if (hw_mgr->devices[dev_type][0]->hw_ops.stop) { rc = hw_mgr->devices[dev_type][0]->hw_ops.stop( Loading drivers/media/platform/msm/camera/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c +1 −0 Original line number Diff line number Diff line Loading @@ -879,6 +879,7 @@ static int cam_lrme_mgr_hw_prepare_update(void *hw_mgr_priv, if (args->num_in_map_entries == 0 || args->num_out_map_entries == 0) { CAM_ERR(CAM_LRME, "Error in port number in %d, out %d", args->num_in_map_entries, args->num_out_map_entries); rc = -EINVAL; goto error; } Loading drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c +40 −8 Original line number Diff line number Diff line Loading @@ -162,6 +162,34 @@ static void __cam_req_mgr_dec_idx(int32_t *val, int32_t step, int32_t max_val) *val = max_val + (*val); } /** * __cam_req_mgr_validate_inject_delay() * * @brief : Check if any pd device is introducing inject delay * @tbl : cam_req_mgr_req_tbl * @curr_idx : slot idx * * @return : 0 for success, negative for failure */ static int __cam_req_mgr_validate_inject_delay( struct cam_req_mgr_req_tbl *tbl, int32_t curr_idx) { struct cam_req_mgr_tbl_slot *slot = NULL; while (tbl) { slot = &tbl->slot[curr_idx]; if (slot->inject_delay > 0) { slot->inject_delay--; return -EAGAIN; } __cam_req_mgr_dec_idx(&curr_idx, tbl->pd_delta, tbl->num_slots); tbl = tbl->next; } return 0; } /** * __cam_req_mgr_traverse() * Loading Loading @@ -201,15 +229,18 @@ static int __cam_req_mgr_traverse(struct cam_req_mgr_traverse *traverse_data) tbl->skip_traverse, traverse_data->in_q->slot[curr_idx].status, traverse_data->in_q->slot[curr_idx].skip_idx); if ((slot->inject_delay > 0) && (traverse_data->self_link == true)) { if ((traverse_data->self_link == true) && (!traverse_data->inject_delay_chk)) { rc = __cam_req_mgr_validate_inject_delay(tbl, curr_idx); if (rc) { CAM_DBG(CAM_CRM, "Injecting Delay of one frame"); apply_data[tbl->pd].req_id = -1; slot->inject_delay--; /* This pd table is not ready to proceed with asked idx */ /* This pd tbl not ready to proceed with asked idx */ SET_FAILURE_BIT(traverse_data->result, tbl->pd); return -EAGAIN; } traverse_data->inject_delay_chk = true; } /* Check if req is ready or in skip mode or pd tbl is in skip mode */ if (tbl->slot[curr_idx].state == CRM_REQ_STATE_READY || Loading Loading @@ -519,6 +550,7 @@ static int __cam_req_mgr_check_link_is_ready(struct cam_req_mgr_core_link *link, traverse_data.result = 0; traverse_data.validate_only = validate_only; traverse_data.self_link = self_link; traverse_data.inject_delay_chk = false; traverse_data.open_req_cnt = link->open_req_cnt; /* * Traverse through all pd tables, if result is success, Loading Loading
drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c +13 −1 Original line number Diff line number Diff line Loading @@ -503,6 +503,18 @@ static void __cam_isp_ctx_send_sof_timestamp( } static int __cam_isp_ctx_reg_upd_in_epoch_state( struct cam_isp_context *ctx_isp, void *evt_data) { if (ctx_isp->frame_id == 1) CAM_DBG(CAM_ISP, "Reg update for early PCR"); else CAM_WARN(CAM_ISP, "Unexpected reg update in activated substate:%d for frame_id:%lld", ctx_isp->substate_activated, ctx_isp->frame_id); return 0; } static int __cam_isp_ctx_reg_upd_in_activated_state( struct cam_isp_context *ctx_isp, void *evt_data) { Loading Loading @@ -1118,7 +1130,7 @@ static struct cam_isp_ctx_irq_ops .irq_ops = { __cam_isp_ctx_handle_error, __cam_isp_ctx_sof_in_epoch, NULL, __cam_isp_ctx_reg_upd_in_epoch_state, __cam_isp_ctx_notify_sof_in_activated_state, __cam_isp_ctx_notify_eof_in_activated_state, __cam_isp_ctx_buf_done_in_epoch, Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c +12 −2 Original line number Diff line number Diff line Loading @@ -204,6 +204,9 @@ static int cam_vfe_camif_resource_start( { struct cam_vfe_mux_camif_data *rsrc_data; uint32_t val = 0; uint32_t epoch0_irq_mask; uint32_t epoch1_irq_mask; uint32_t computed_epoch_line_cfg; if (!camif_res) { CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); Loading Loading @@ -243,9 +246,16 @@ static int cam_vfe_camif_resource_start( rsrc_data->common_reg->module_ctrl[ CAM_VFE_TOP_VER2_MODULE_STATS]->cgc_ovd); /* epoch config with 20 line */ cam_io_w_mb(rsrc_data->reg_data->epoch_line_cfg, /* epoch config */ epoch0_irq_mask = ((rsrc_data->last_line - rsrc_data->first_line) / 2) + rsrc_data->first_line; epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg & 0xFFFF; computed_epoch_line_cfg = (epoch0_irq_mask << 16) | epoch1_irq_mask; cam_io_w_mb(computed_epoch_line_cfg, rsrc_data->mem_base + rsrc_data->camif_reg->epoch_irq); CAM_DBG(CAM_ISP, "first_line:%u last_line:%u epoch_line_cfg: 0x%x", rsrc_data->first_line, rsrc_data->last_line, computed_epoch_line_cfg); camif_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; Loading
drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +0 −7 Original line number Diff line number Diff line Loading @@ -770,13 +770,6 @@ static int cam_jpeg_mgr_flush(void *hw_mgr_priv, } else { CAM_ERR(CAM_JPEG, "process_cmd null "); } rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd( hw_mgr->devices[dev_type][0]->hw_priv, CAM_JPEG_CMD_SET_IRQ_CB, &irq_cb, sizeof(irq_cb)); if (rc) CAM_ERR(CAM_JPEG, "CMD_SET_IRQ_CB failed %d", rc); if (hw_mgr->devices[dev_type][0]->hw_ops.stop) { rc = hw_mgr->devices[dev_type][0]->hw_ops.stop( Loading
drivers/media/platform/msm/camera/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c +1 −0 Original line number Diff line number Diff line Loading @@ -879,6 +879,7 @@ static int cam_lrme_mgr_hw_prepare_update(void *hw_mgr_priv, if (args->num_in_map_entries == 0 || args->num_out_map_entries == 0) { CAM_ERR(CAM_LRME, "Error in port number in %d, out %d", args->num_in_map_entries, args->num_out_map_entries); rc = -EINVAL; goto error; } Loading
drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c +40 −8 Original line number Diff line number Diff line Loading @@ -162,6 +162,34 @@ static void __cam_req_mgr_dec_idx(int32_t *val, int32_t step, int32_t max_val) *val = max_val + (*val); } /** * __cam_req_mgr_validate_inject_delay() * * @brief : Check if any pd device is introducing inject delay * @tbl : cam_req_mgr_req_tbl * @curr_idx : slot idx * * @return : 0 for success, negative for failure */ static int __cam_req_mgr_validate_inject_delay( struct cam_req_mgr_req_tbl *tbl, int32_t curr_idx) { struct cam_req_mgr_tbl_slot *slot = NULL; while (tbl) { slot = &tbl->slot[curr_idx]; if (slot->inject_delay > 0) { slot->inject_delay--; return -EAGAIN; } __cam_req_mgr_dec_idx(&curr_idx, tbl->pd_delta, tbl->num_slots); tbl = tbl->next; } return 0; } /** * __cam_req_mgr_traverse() * Loading Loading @@ -201,15 +229,18 @@ static int __cam_req_mgr_traverse(struct cam_req_mgr_traverse *traverse_data) tbl->skip_traverse, traverse_data->in_q->slot[curr_idx].status, traverse_data->in_q->slot[curr_idx].skip_idx); if ((slot->inject_delay > 0) && (traverse_data->self_link == true)) { if ((traverse_data->self_link == true) && (!traverse_data->inject_delay_chk)) { rc = __cam_req_mgr_validate_inject_delay(tbl, curr_idx); if (rc) { CAM_DBG(CAM_CRM, "Injecting Delay of one frame"); apply_data[tbl->pd].req_id = -1; slot->inject_delay--; /* This pd table is not ready to proceed with asked idx */ /* This pd tbl not ready to proceed with asked idx */ SET_FAILURE_BIT(traverse_data->result, tbl->pd); return -EAGAIN; } traverse_data->inject_delay_chk = true; } /* Check if req is ready or in skip mode or pd tbl is in skip mode */ if (tbl->slot[curr_idx].state == CRM_REQ_STATE_READY || Loading Loading @@ -519,6 +550,7 @@ static int __cam_req_mgr_check_link_is_ready(struct cam_req_mgr_core_link *link, traverse_data.result = 0; traverse_data.validate_only = validate_only; traverse_data.self_link = self_link; traverse_data.inject_delay_chk = false; traverse_data.open_req_cnt = link->open_req_cnt; /* * Traverse through all pd tables, if result is success, Loading