Merge "ARM: dts: msm: Add QUPV3 SE dt node for uart on sdm640" into msm-4.14 (7a834a8c) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sdm640-cdp.dtsi

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		@@ -19,5 +19,33 @@
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;

		qupv3_se0_2uart_pins: qupv3_se0_2uart_pins {
		qupv3_se0_2uart_active: qupv3_se0_2uart_active {
		mux {
		pins = "gpio16", "gpio17";
		function = "qup00";
		};

		config {
		pins = "gpio16", "gpio17";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se0_2uart_sleep: qupv3_se0_2uart_sleep {
		mux {
		pins = "gpio16", "gpio17";
		function = "gpio";
		};

		config {
		pins = "gpio16", "gpio17";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};
		};
		};

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		/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <dt-bindings/msm/msm-bus-ids.h>

		&soc {
		/* QUPv3 North Instances */
		qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x8c0000 0x6000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_1>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		};

		/* Debug UART Instance for CDP/MTP platform */
		qupv3_se0_2uart: qcom,qup_uart@0x880000 {
		compatible = "qcom,msm-geni-console";
		reg = <0x880000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_2uart_active>;
		pinctrl-1 = <&qupv3_se0_2uart_sleep>;
		interrupts = <GIC_SPI 601 0>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};
		};

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