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Commit 79daedc9 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: minor pm cleanups 



- remove non_clock_info struct
- track power state misc flags

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent d91eeb78

drivers/gpu/drm/radeon/r100.c

+1 −1
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ void r100_get_power_state(struct radeon_device *rdev, 
		 rdev->pm.power_state[rdev->pm.requested_power_state_index].

		 clock_info[rdev->pm.requested_clock_mode_index].mclk,

		 rdev->pm.power_state[rdev->pm.requested_power_state_index].

		 non_clock_info.pcie_lanes);

		 pcie_lanes);

}



void r100_set_power_state(struct radeon_device *rdev)

drivers/gpu/drm/radeon/r600.c

+1 −1
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ void r600_get_power_state(struct radeon_device *rdev, 
		 rdev->pm.power_state[rdev->pm.requested_power_state_index].

		 clock_info[rdev->pm.requested_clock_mode_index].mclk,

		 rdev->pm.power_state[rdev->pm.requested_power_state_index].

		 non_clock_info.pcie_lanes);

		 pcie_lanes);

}



void r600_set_power_state(struct radeon_device *rdev)

drivers/gpu/drm/radeon/radeon.h

+3 −10
Original line number Diff line number Diff line
@@ -654,13 +654,6 @@ struct radeon_voltage { 
	u32 voltage;

};



struct radeon_pm_non_clock_info {

	/* pcie lanes */

	int pcie_lanes;

	/* standardized non-clock flags */

	u32 flags;

};



struct radeon_pm_clock_info {

	/* memory clock */

	u32 mclk;
@@ -682,11 +675,11 @@ struct radeon_power_state { 
	/* number of valid clock modes in this power state */

	int num_clock_modes;

	struct radeon_pm_clock_info *default_clock_mode;

	/* non clock info about this state */

	struct radeon_pm_non_clock_info non_clock_info;

	bool voltage_drop_active;

	/* standardized state flags */

	u32 flags;

	u32 misc; /* vbios specific flags */

	u32 misc2; /* vbios specific flags */

	int pcie_lanes; /* pcie lanes */

};



/*

drivers/gpu/drm/radeon/radeon_atombios.c

+14 −8
Original line number Diff line number Diff line
@@ -1528,7 +1528,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) 
					if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||

					    (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))

						continue;

					rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =

					rdev->pm.power_state[state_index].pcie_lanes =

						power_info->info.asPowerPlayInfo[i].ucNumPciELanes;

					misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);

					if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
@@ -1550,6 +1550,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) 
							power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;

					}

					rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;

					rdev->pm.power_state[state_index].misc = misc;

					/* order matters! */

					if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)

						rdev->pm.power_state[state_index].type =
@@ -1590,7 +1591,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) 
					if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||

					    (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))

						continue;

					rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =

					rdev->pm.power_state[state_index].pcie_lanes =

						power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;

					misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);

					misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
@@ -1613,6 +1614,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) 
							power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;

					}

					rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;

					rdev->pm.power_state[state_index].misc = misc;

					rdev->pm.power_state[state_index].misc2 = misc2;

					/* order matters! */

					if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)

						rdev->pm.power_state[state_index].type =
@@ -1659,7 +1662,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) 
					if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||

					    (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))

						continue;

					rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =

					rdev->pm.power_state[state_index].pcie_lanes =

						power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;

					misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);

					misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
@@ -1688,6 +1691,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) 
						}

					}

					rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;

					rdev->pm.power_state[state_index].misc = misc;

					rdev->pm.power_state[state_index].misc2 = misc2;

					/* order matters! */

					if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)

						rdev->pm.power_state[state_index].type =
@@ -1730,6 +1735,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) 
					&rdev->pm.power_state[state_index - 1].clock_info[0];

				rdev->pm.power_state[state_index].flags &=

					~RADEON_PM_SINGLE_DISPLAY_ONLY;

				rdev->pm.power_state[state_index].misc = 0;

				rdev->pm.power_state[state_index].misc2 = 0;

			}

		} else {

			/* add the i2c bus for thermal/fan chip */
@@ -1852,7 +1859,9 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) 
				if (mode_index) {

					misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);

					misc2 = le16_to_cpu(non_clock_info->usClassification);

					rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =

					rdev->pm.power_state[state_index].misc = misc;

					rdev->pm.power_state[state_index].misc2 = misc2;

					rdev->pm.power_state[state_index].pcie_lanes =

						((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>

						ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;

					switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
@@ -1902,10 +1911,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) 
		rdev->pm.power_state[state_index].default_clock_mode =

			&rdev->pm.power_state[state_index].clock_info[0];

		rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;

		if (rdev->asic->get_pcie_lanes)

			rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);

		else

			rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;

		rdev->pm.power_state[state_index].pcie_lanes = 16;

		rdev->pm.default_power_state_index = state_index;

		rdev->pm.power_state[state_index].flags = 0;

		state_index++;

drivers/gpu/drm/radeon/radeon_combios.c

+4 −11
Original line number Diff line number Diff line
@@ -2382,17 +2382,13 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) 
			if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||

			    (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))

				goto default_mode;

			/* skip overclock modes for now */

			if ((rdev->pm.power_state[state_index].clock_info[0].mclk >

			     rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||

			    (rdev->pm.power_state[state_index].clock_info[0].sclk >

			     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))

				goto default_mode;

			rdev->pm.power_state[state_index].type =

				POWER_STATE_TYPE_BATTERY;

			misc = RBIOS16(offset + 0x5 + 0x0);

			if (rev > 4)

				misc2 = RBIOS16(offset + 0x5 + 0xe);

			rdev->pm.power_state[state_index].misc = misc;

			rdev->pm.power_state[state_index].misc2 = misc2;

			if (misc & 0x4) {

				rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;

				if (misc & 0x8)
@@ -2439,7 +2435,7 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) 
			} else

				rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;

			if (rev > 6)

				rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =

				rdev->pm.power_state[state_index].pcie_lanes =

					RBIOS8(offset + 0x5 + 0x10);

			rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;

			state_index++;
@@ -2459,10 +2455,7 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) 
	rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;

	rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];

	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;

	if (rdev->asic->get_pcie_lanes)

		rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);

	else

		rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;

	rdev->pm.power_state[state_index].pcie_lanes = 16;

	rdev->pm.power_state[state_index].flags = 0;

	rdev->pm.default_power_state_index = state_index;

	rdev->pm.num_power_states = state_index + 1;