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Commit 79cbb153 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Enable IFPC on A640 v1"

parents 99de8549 81f003e0

drivers/gpu/msm/adreno-gpulist.h

+2 −1
Original line number Diff line number Diff line
@@ -386,7 +386,8 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.minor = 0,

		.patchid = 0,

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU |

			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT,

			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a640_zap",

		.gpudev = &adreno_a6xx_gpudev,

drivers/gpu/msm/adreno.c

+11 −2
Original line number Diff line number Diff line
@@ -3261,7 +3261,7 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev, 
	if (!gmu_core_isenabled(KGSL_DEVICE(adreno_dev)))

		return 0;



	for (i = 0; i < GMU_CORE_WAKEUP_RETRY_MAX; i++) {

	for (i = 0; i < GMU_CORE_LONG_WAKEUP_RETRY_LIMIT; i++) {

		adreno_read_gmureg(adreno_dev, ADRENO_REG_GMU_AHB_FENCE_STATUS,

			&status);
@@ -3276,10 +3276,19 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev, 


		/* Try to write the fenced register again */

		adreno_writereg(adreno_dev, offset, val);



		if (i == GMU_CORE_SHORT_WAKEUP_RETRY_LIMIT)

			dev_err(adreno_dev->dev.dev,

				"Waited %d usecs to write fenced register 0x%x. Continuing to wait...\n",

				(GMU_CORE_SHORT_WAKEUP_RETRY_LIMIT *

				GMU_CORE_WAKEUP_DELAY_US),

				reg_offset);

	}



	dev_err(adreno_dev->dev.dev,

		"GMU fenced register write timed out: reg 0x%x\n", reg_offset);

		"Timed out waiting %d usecs to write fenced register 0x%x\n",

		GMU_CORE_LONG_WAKEUP_RETRY_LIMIT * GMU_CORE_WAKEUP_DELAY_US,

		reg_offset);

	return -ETIMEDOUT;

}

drivers/gpu/msm/kgsl_gmu_core.h

+9 −2
Original line number Diff line number Diff line
@@ -100,8 +100,15 @@ enum gpu_idle_level { 
 * the GMU will start shutting down before we try again.

 */

#define GMU_CORE_WAKEUP_DELAY_US 10

/* Max amount of tries to wake up the GMU. */

#define GMU_CORE_WAKEUP_RETRY_MAX 60



/* Max amount of tries to wake up the GMU. The short retry

 * limit is half of the long retry limit. After the short

 * number of retries, we print an informational message to say

 * exiting IFPC is taking longer than expected. We continue

 * to retry after this until the long retry limit.

 */

#define GMU_CORE_SHORT_WAKEUP_RETRY_LIMIT 100

#define GMU_CORE_LONG_WAKEUP_RETRY_LIMIT 200



#define FENCE_STATUS_WRITEDROPPED0_MASK 0x1

#define FENCE_STATUS_WRITEDROPPED1_MASK 0x2