Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 79301893 authored by Akhil P Oommen's avatar Akhil P Oommen
Browse files

ARM: dts: msm: Add GPU properties for sdmmagpie 



Add device-specific GPU properties for sdmmagpie.
Add GPU clocks, registers, interrupts, bus,
freq plan, SMMU properties, and GPU power levels.

Change-Id: I84de4c8118ff0c8a1c0a99dd55ef3323220ff094
Signed-off-by: default avatarAkhil P Oommen <akhilpo@codeaurora.org>
parent 174fd57a

arch/arm64/boot/dts/qcom/sdmmagpie-gpu.dtsi

0 → 100644
+607 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {



	pil_gpu: qcom,kgsl-hyp {

		compatible = "qcom,pil-tz-generic";

		qcom,pas-id = <13>;

		qcom,firmware-name = "a615_zap";

	};



	msm_bus: qcom,kgsl-busmon{

		label = "kgsl-busmon";

		compatible = "qcom,kgsl-busmon";

	};



	gpu_bw_tbl: gpu-bw-tbl {

		compatible = "operating-points-v2";

		opp-0    { opp-hz = /bits/ 64 < 0 >;    }; /*  OFF */

		opp-100  { opp-hz = /bits/ 64 < 381 >;  }; /*  1.DDR:100 MHz */

		opp-200  { opp-hz = /bits/ 64 < 762 >;  }; /*  2.DDR:200 MHz */

		opp-300  { opp-hz = /bits/ 64 < 1144 >; }; /*  3.DDR:300 MHz */

		opp-451  { opp-hz = /bits/ 64 < 1720 >; }; /*  4.DDR:451 MHz */

		opp-547  { opp-hz = /bits/ 64 < 2086 >; }; /*  5.DDR:547 MHz */

		opp-681  { opp-hz = /bits/ 64 < 2597 >; }; /*  6.DDR:681 MHz */

		opp-825  { opp-hz = /bits/ 64 < 3147 >; }; /*  7.DDR:825 MHz */

		opp-1017 { opp-hz = /bits/ 64 < 3879 >; }; /*  8.DDR:1017 MHz */

		opp-1353 { opp-hz = /bits/ 64 < 5161 >; }; /*  9.DDR:1353 MHz */

		opp-1555 { opp-hz = /bits/ 64 < 5931 >; }; /* 10.DDR:1555 MHz */

		opp-1804 { opp-hz = /bits/ 64 < 6881 >; }; /* 11.DDR:1804 MHz */

	};



	gpubw: qcom,gpubw {

		compatible = "qcom,devbw";

		governor = "bw_vbif";

		qcom,src-dst-ports = <26 512>;

		operating-points-v2 = <&gpu_bw_tbl>;

	};



	msm_gpu: qcom,kgsl-3d0@5000000 {

		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		status = "ok";

		reg =   <0x5000000 0x40000>,

			<0x5061000 0x800>,

			<0x780000 0x6300>;

		reg-names =     "kgsl_3d0_reg_memory",

				"kgsl_3d0_cx_dbgc_memory",

				"qfprom_memory";

		interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;



		qcom,chipid = <0x06010800>;



		qcom,gpu-quirk-hfi-use-reg;

		qcom,gpu-quirk-secvid-set-once;



		/* <HZ/12> */

		qcom,idle-timeout = <80>;

		qcom,no-nap;



		qcom,highest-bank-bit = <14>;



		qcom,min-access-length = <32>;



		qcom,ubwc-mode = <2>;



		/* size in bytes */

		qcom,snapshot-size = <1048576>;



		/* base addr, size */

		qcom,gpu-qdss-stm = <0x161c0000 0x40000>;

		#cooling-cells = <2>;



		clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK>,

			<&clock_gpucc GPU_CC_CXO_CLK>,

			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,

			<&clock_gpucc GPU_CC_CX_GMU_CLK>;



		clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",

				"mem_iface_clk", "gmu_clk";



		/* Bus Scale Settings */

		qcom,gpubw-dev = <&gpubw>;

		qcom,bus-control;

		qcom,msm-bus,name = "grp3d";

		qcom,bus-width = <32>;

		qcom,msm-bus,num-cases = <12>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<26 512 0 0>,

				<26 512 0 400000>,     /*  1 bus=100  */

				<26 512 0 800000>,     /*  2 bus=200  */

				<26 512 0 1200000>,    /*  3 bus=300  */

				<26 512 0 1804000>,    /*  4 bus=451  */

				<26 512 0 2188000>,    /*  5 bus=547  */

				<26 512 0 2724000>,    /*  6 bus=681  */

				<26 512 0 3300000>,    /*  7 bus=825  */

				<26 512 0 4068000>,    /*  8 bus=1017 */

				<26 512 0 5412000>,    /*  9 bus=1353 */

				<26 512 0 6220000>,    /* 10 bus=1555 */

				<26 512 0 7216000>;    /* 11 bus=1804 */



		/* GDSC regulator names */

		regulator-names = "vddcx", "vdd";

		/* GDSC oxili regulators */

		vddcx-supply = <&gpu_cx_gdsc>;

		vdd-supply = <&gpu_gx_gdsc>;



		/* GPU related llc slices */

		cache-slice-names = "gpu", "gpuhtw";

		cache-slices = <&llcc 12>, <&llcc 11>;



		/* CPU latency parameter */

		qcom,pm-qos-active-latency = <67>;

		qcom,pm-qos-wakeup-latency = <67>;



		/* Enable context aware freq. scaling */

		qcom,enable-ca-jump;

		/* Context aware jump busy penalty in us */

		qcom,ca-busy-penalty = <12000>;



		qcom,gpu-speed-bin = <0x41a0 0x1fe00000 21>;



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

				qcom,mempool-allocate;

			};

			/* 8K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size = <8192>;

				qcom,mempool-allocate;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@2 {

				reg = <2>;

				qcom,mempool-page-size = <65536>;

				qcom,mempool-reserved = <256>;

			};

			/* 1M Page Pool configuration */

			qcom,gpu-mempool@3 {

				reg = <3>;

				qcom,mempool-page-size = <1048576>;

				qcom,mempool-reserved = <32>;

			};

		};



		/*

		 * Speed-bin zero is default speed bin.

		 * For rest of the speed bins, speed-bin value

		 * is calulated as FMAX/4.8 MHz round up to zero

		 * decimal places.

		 */

		qcom,gpu-pwrlevel-bins {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible="qcom,gpu-pwrlevel-bins";



			qcom,gpu-pwrlevels-0 {

				#address-cells = <1>;

				#size-cells = <0>;



				qcom,speed-bin = <0>;



				qcom,initial-pwrlevel = <7>;

				qcom,ca-target-pwrlevel = <5>;



				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <825000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <10>;

					qcom,bus-max = <11>;

				};



				/* TURBO */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <800000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <10>;

					qcom,bus-max = <11>;

				};



				/* NOM_L1 */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <650000000>;

					qcom,bus-freq = <10>;

					qcom,bus-min = <8>;

					qcom,bus-max = <11>;

				};



				/* NOM */

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <565000000>;

					qcom,bus-freq = <9>;

					qcom,bus-min = <8>;

					qcom,bus-max = <10>;

				};



				/* SVS_L1 */

				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <430000000>;

					qcom,bus-freq = <8>;

					qcom,bus-min = <7>;

					qcom,bus-max = <10>;

				};



				/* SVS */

				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <355000000>;

					qcom,bus-freq = <7>;

					qcom,bus-min = <5>;

					qcom,bus-max = <8>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@6 {

					reg = <6>;

					qcom,gpu-freq = <267000000>;

					qcom,bus-freq = <6>;

					qcom,bus-min = <4>;

					qcom,bus-max = <7>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@7 {

					reg = <7>;

					qcom,gpu-freq = <180000000>;

					qcom,bus-freq = <4>;

					qcom,bus-min = <3>;

					qcom,bus-max = <4>;

				};



				/* XO */

				qcom,gpu-pwrlevel@8 {

					reg = <8>;

					qcom,gpu-freq = <0>;

					qcom,bus-freq = <0>;

					qcom,bus-min = <0>;

					qcom,bus-max = <0>;

				};

			};



			qcom,gpu-pwrlevels-1 {

				#address-cells = <1>;

				#size-cells = <0>;



				qcom,speed-bin = <172>;



				qcom,initial-pwrlevel = <7>;

				qcom,ca-target-pwrlevel = <5>;



				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <825000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <10>;

					qcom,bus-max = <11>;

				};



				/* TURBO */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <800000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <10>;

					qcom,bus-max = <11>;

				};



				/* NOM_L1 */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <650000000>;

					qcom,bus-freq = <10>;

					qcom,bus-min = <8>;

					qcom,bus-max = <11>;

				};



				/* NOM */

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <565000000>;

					qcom,bus-freq = <9>;

					qcom,bus-min = <8>;

					qcom,bus-max = <10>;

				};



				/* SVS_L1 */

				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <430000000>;

					qcom,bus-freq = <8>;

					qcom,bus-min = <7>;

					qcom,bus-max = <10>;

				};



				/* SVS */

				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <355000000>;

					qcom,bus-freq = <7>;

					qcom,bus-min = <5>;

					qcom,bus-max = <8>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@6 {

					reg = <6>;

					qcom,gpu-freq = <267000000>;

					qcom,bus-freq = <6>;

					qcom,bus-min = <4>;

					qcom,bus-max = <7>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@7 {

					reg = <7>;

					qcom,gpu-freq = <180000000>;

					qcom,bus-freq = <4>;

					qcom,bus-min = <3>;

					qcom,bus-max = <4>;

				};



				/* XO */

				qcom,gpu-pwrlevel@8 {

					reg = <8>;

					qcom,gpu-freq = <0>;

					qcom,bus-freq = <0>;

					qcom,bus-min = <0>;

					qcom,bus-max = <0>;

				};

			};



			qcom,gpu-pwrlevels-2 {

				#address-cells = <1>;

				#size-cells = <0>;



				qcom,speed-bin = <146>;



				qcom,initial-pwrlevel = <6>;

				qcom,ca-target-pwrlevel = <4>;



				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <700000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <10>;

					qcom,bus-max = <11>;

				};



				/* NOM_L1 */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <650000000>;

					qcom,bus-freq = <10>;

					qcom,bus-min = <8>;

					qcom,bus-max = <11>;

				};



				/* NOM */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <565000000>;

					qcom,bus-freq = <9>;

					qcom,bus-min = <8>;

					qcom,bus-max = <10>;

				};



				/* SVS_L1 */

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <430000000>;

					qcom,bus-freq = <8>;

					qcom,bus-min = <7>;

					qcom,bus-max = <10>;

				};



				/* SVS */

				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <355000000>;

					qcom,bus-freq = <7>;

					qcom,bus-min = <5>;

					qcom,bus-max = <8>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <267000000>;

					qcom,bus-freq = <6>;

					qcom,bus-min = <4>;

					qcom,bus-max = <7>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@6 {

					reg = <6>;

					qcom,gpu-freq = <180000000>;

					qcom,bus-freq = <4>;

					qcom,bus-min = <3>;

					qcom,bus-max = <4>;

				};



				/* XO */

				qcom,gpu-pwrlevel@7 {

					reg = <7>;

					qcom,gpu-freq = <0>;

					qcom,bus-freq = <0>;

					qcom,bus-min = <0>;

					qcom,bus-max = <0>;

				};

			};



			qcom,gpu-pwrlevels-3 {

				#address-cells = <1>;

				#size-cells = <0>;



				qcom,speed-bin = <128>;



				qcom,initial-pwrlevel = <5>;

				qcom,ca-target-pwrlevel = <3>;



				/* NOM_L1 */

				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <610000000>;

					qcom,bus-freq = <11>;

					qcom,bus-min = <10>;

					qcom,bus-max = <11>;

				};



				/* NOM */

				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <565000000>;

					qcom,bus-freq = <9>;

					qcom,bus-min = <8>;

					qcom,bus-max = <10>;

				};



				/* SVS_L1 */

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <430000000>;

					qcom,bus-freq = <8>;

					qcom,bus-min = <7>;

					qcom,bus-max = <10>;

				};



				/* SVS */

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <355000000>;

					qcom,bus-freq = <7>;

					qcom,bus-min = <5>;

					qcom,bus-max = <8>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <267000000>;

					qcom,bus-freq = <6>;

					qcom,bus-min = <4>;

					qcom,bus-max = <7>;

				};



				/* LOW SVS */

				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <180000000>;

					qcom,bus-freq = <4>;

					qcom,bus-min = <3>;

					qcom,bus-max = <4>;

				};



				/* XO */

				qcom,gpu-pwrlevel@6 {

					reg = <6>;

					qcom,gpu-freq = <0>;

					qcom,bus-freq = <0>;

					qcom,bus-min = <0>;

					qcom,bus-max = <0>;

				};

			};

		};

	};



	kgsl_msm_iommu: qcom,kgsl-iommu@5040000 {

		compatible = "qcom,kgsl-smmu-v2";



		reg = <0x05040000 0x10000>;

		qcom,protect = <0x40000 0x10000>;

		qcom,micro-mmu-control = <0x6000>;



		clocks = <&clock_gcc GCC_GPU_CFG_AHB_CLK>,

			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;



		clock-names = "iface_clk", "mem_clk", "mem_iface_clk";



		qcom,secure_align_mask = <0xfff>;

		qcom,retention;

		qcom,hyp_secure_alloc;



		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_user";

			iommus = <&kgsl_smmu 0>;

			qcom,gpu-offset = <0x48000>;

		};



		gfx3d_secure: gfx3d_secure {

			compatible = "qcom,smmu-kgsl-cb";

			iommus = <&kgsl_smmu 2>;

		};

	};



	gmu: qcom,gmu@506a000 {

		label = "kgsl-gmu";

		compatible = "qcom,gpu-gmu";



		reg = <0x506a000 0x31000>,

			<0xb290000 0x10000>,

			<0xb490000 0x10000>;

		reg-names = "kgsl_gmu_reg",

			"kgsl_gmu_pdc_cfg",

			"kgsl_gmu_pdc_seq";



		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,

				<0 305 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";



		qcom,msm-bus,name = "cnoc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<26 10036 0 0>,      /* CNOC off */

			<26 10036 0 100>;    /* CNOC on  */



		regulator-names = "vddcx", "vdd";

		vddcx-supply = <&gpu_cx_gdsc>;

		vdd-supply = <&gpu_gx_gdsc>;



		clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,

				<&clock_gpucc GPU_CC_CXO_CLK>,

				<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

				<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;



		clock-names = "gmu_clk", "cxo_clk", "axi_clk",

				"memnoc_clk";



		qcom,gmu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,gmu-pwrlevels";



			qcom,gmu-pwrlevel@0 {

				reg = <0>;

				qcom,gmu-freq = <0>;

			};



			qcom,gmu-pwrlevel@1 {

				reg = <1>;

				qcom,gmu-freq = <200000000>;

			};

		};



		gmu_user: gmu_user {

			compatible = "qcom,smmu-gmu-user-cb";

			iommus = <&kgsl_smmu 4>;

		};



		gmu_kernel: gmu_kernel {

			compatible = "qcom,smmu-gmu-kernel-cb";

			iommus = <&kgsl_smmu 5>;

		};

	};

};

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+1 −6
Original line number Diff line number Diff line
@@ -583,12 +583,6 @@ 
			reg = <0 0x95a10000 0 0x5000>;

		};



		pil_gpu_mem: gpu_region@95a15000 {

			compatible = "removed-dma-pool";

			no-map;

			reg = <0 0x95a15000 0 0x2000>;

		};



		npu_mem: npu_region@95a80000 {

			compatible = "removed-dma-pool";

			no-map;
@@ -3063,6 +3057,7 @@ 
};



#include "sdmmagpie-audio.dtsi"

#include "sdmmagpie-gpu.dtsi"



&usb0 {

	extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>;