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Commit 78f9f3b1 authored by Sebastian Hesselbarth's avatar Sebastian Hesselbarth Committed by Jason Cooper
Browse files

pinctrl: mvebu: fix iomem pointer for dove pinctrl 



There has been a change in readl/writel to require registers
addresses marked as IOMEM(). This patch takes care of this and
also replaces ORing address offsets with adding them.

Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 423b8959

drivers/pinctrl/mvebu/pinctrl-dove.c

+7 −7
Original line number Diff line number Diff line
@@ -22,22 +22,22 @@ 


#include "pinctrl-mvebu.h"



#define DOVE_SB_REGS_VIRT_BASE		0xfde00000

#define DOVE_MPP_VIRT_BASE		(DOVE_SB_REGS_VIRT_BASE | 0xd0200)

#define DOVE_SB_REGS_VIRT_BASE		IOMEM(0xfde00000)

#define DOVE_MPP_VIRT_BASE		(DOVE_SB_REGS_VIRT_BASE + 0xd0200)

#define DOVE_PMU_MPP_GENERAL_CTRL	(DOVE_MPP_VIRT_BASE + 0x10)

#define  DOVE_AU0_AC97_SEL		BIT(16)

#define DOVE_GLOBAL_CONFIG_1		(DOVE_SB_REGS_VIRT_BASE | 0xe802C)

#define DOVE_GLOBAL_CONFIG_1		(DOVE_SB_REGS_VIRT_BASE + 0xe802C)

#define  DOVE_TWSI_ENABLE_OPTION1	BIT(7)

#define DOVE_GLOBAL_CONFIG_2		(DOVE_SB_REGS_VIRT_BASE | 0xe8030)

#define DOVE_GLOBAL_CONFIG_2		(DOVE_SB_REGS_VIRT_BASE + 0xe8030)

#define  DOVE_TWSI_ENABLE_OPTION2	BIT(20)

#define  DOVE_TWSI_ENABLE_OPTION3	BIT(21)

#define  DOVE_TWSI_OPTION3_GPIO		BIT(22)

#define DOVE_SSP_CTRL_STATUS_1		(DOVE_SB_REGS_VIRT_BASE | 0xe8034)

#define DOVE_SSP_CTRL_STATUS_1		(DOVE_SB_REGS_VIRT_BASE + 0xe8034)

#define  DOVE_SSP_ON_AU1		BIT(0)

#define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xe803c)

#define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe803c)

#define  DOVE_AU1_SPDIFO_GPIO_EN	BIT(1)

#define  DOVE_NAND_GPIO_EN		BIT(0)

#define DOVE_GPIO_LO_VIRT_BASE		(DOVE_SB_REGS_VIRT_BASE | 0xd0400)

#define DOVE_GPIO_LO_VIRT_BASE		(DOVE_SB_REGS_VIRT_BASE + 0xd0400)

#define DOVE_MPP_CTRL4_VIRT_BASE	(DOVE_GPIO_LO_VIRT_BASE + 0x40)

#define  DOVE_SPI_GPIO_SEL		BIT(5)

#define  DOVE_UART1_GPIO_SEL		BIT(4)