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Commit 78f90dcf authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

tg3: Move napi_add calls below tg3_get_invariants 



tg3_get_invariants(), among other things, discovers whether or not
the device is MSI-X capable and how many interrupts it supports.
This discovery needs to happen before registering NAPI instances with
netdev.  This patch moves the code block that calls napi_add later in
tg3_init_one() so that tg3_get_invariants() has a chance to run first.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Reviewed-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 35f2d7d0

drivers/net/tg3.c

+47 −47
Original line number Diff line number Diff line
@@ -14089,53 +14089,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, 
	tp->rx_pending = TG3_DEF_RX_RING_PENDING;

	tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;



	intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;

	rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;

	sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;

	for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {

		struct tg3_napi *tnapi = &tp->napi[i];



		tnapi->tp = tp;

		tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;



		tnapi->int_mbox = intmbx;

		if (i < 4)

			intmbx += 0x8;

		else

			intmbx += 0x4;



		tnapi->consmbox = rcvmbx;

		tnapi->prodmbox = sndmbx;



		if (i) {

			tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);

			netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);

		} else {

			tnapi->coal_now = HOSTCC_MODE_NOW;

			netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);

		}



		if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))

			break;



		/*

		 * If we support MSIX, we'll be using RSS.  If we're using

		 * RSS, the first vector only handles link interrupts and the

		 * remaining vectors handle rx and tx interrupts.  Reuse the

		 * mailbox values for the next iteration.  The values we setup

		 * above are still useful for the single vectored mode.

		 */

		if (!i)

			continue;



		rcvmbx += 0x8;



		if (sndmbx & 0x4)

			sndmbx -= 0x4;

		else

			sndmbx += 0xc;

	}



	dev->ethtool_ops = &tg3_ethtool_ops;

	dev->watchdog_timeo = TG3_TX_TIMEOUT;

	dev->irq = pdev->irq;
@@ -14278,6 +14231,53 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, 
	tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;

	tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;



	intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;

	rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;

	sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;

	for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {

		struct tg3_napi *tnapi = &tp->napi[i];



		tnapi->tp = tp;

		tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;



		tnapi->int_mbox = intmbx;

		if (i < 4)

			intmbx += 0x8;

		else

			intmbx += 0x4;



		tnapi->consmbox = rcvmbx;

		tnapi->prodmbox = sndmbx;



		if (i) {

			tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);

			netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);

		} else {

			tnapi->coal_now = HOSTCC_MODE_NOW;

			netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);

		}



		if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))

			break;



		/*

		 * If we support MSIX, we'll be using RSS.  If we're using

		 * RSS, the first vector only handles link interrupts and the

		 * remaining vectors handle rx and tx interrupts.  Reuse the

		 * mailbox values for the next iteration.  The values we setup

		 * above are still useful for the single vectored mode.

		 */

		if (!i)

			continue;



		rcvmbx += 0x8;



		if (sndmbx & 0x4)

			sndmbx -= 0x4;

		else

			sndmbx += 0xc;

	}



	tg3_init_coal(tp);



	pci_set_drvdata(pdev, dev);