Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 782cf7d8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux 

Alex writes:
A few more radeon bug fixes, mostly for SI dpm.  At this point dpm is
pretty solid across the majority of asics.  I think we mostly just have
corner cases and fixing up some of the trickier features at this point.

* 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/dpm: fix and enable reclocking on SI
  drm/radeon/dpm: disable cac setup on SI
  drm/radeon/si: disable cgcg and pg for now
  drm/radeon/dpm: fix forcing performance state to low on cayman
  drm/radeon/atom: fix fb when fetching engine params
  drm/radeon: properly handle cg on asics without UVD
  drm/radeon/dpm: fix powertune handling for pci id 0x6835
  drm/radeon/dpm: fix si_calculate_memory_refresh_rate()
  drm/radeon/dpm: fix display gap programming on SI
  drm/radeon: fix audio dto programming on DCE4+
parents 5ae90d8e 63f22d0e

drivers/gpu/drm/radeon/evergreen_hdmi.c

+1 −1
Original line number Diff line number Diff line
@@ -157,9 +157,9 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) 
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

	 */

	WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));

	WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);

	WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);

	WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));

}

drivers/gpu/drm/radeon/ni_dpm.c

+1 −6
Original line number Diff line number Diff line
@@ -1054,10 +1054,6 @@ static int ni_restrict_performance_levels_before_switch(struct radeon_device *rd 
int ni_dpm_force_performance_level(struct radeon_device *rdev,

				   enum radeon_dpm_forced_level level)

{

	struct radeon_ps *rps = rdev->pm.dpm.current_ps;

	struct ni_ps *ps = ni_get_ps(rps);

	u32 levels;



	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {

		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)

			return -EINVAL;
@@ -1068,8 +1064,7 @@ int ni_dpm_force_performance_level(struct radeon_device *rdev, 
		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)

			return -EINVAL;



		levels = ps->performance_level_count - 1;

		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)

		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)

			return -EINVAL;

	} else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {

		if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)

drivers/gpu/drm/radeon/radeon_atombios.c

+1 −1
Original line number Diff line number Diff line
@@ -2782,7 +2782,7 @@ int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 
							     ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;

				dividers->enable_dithen = (args.v3.ucCntlFlag &

							   ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;

				dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);

				dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);

				dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);

				dividers->ref_div = args.v3.ucRefDiv;

				dividers->vco_mode = (args.v3.ucCntlFlag &

drivers/gpu/drm/radeon/si.c

+5 −9
Original line number Diff line number Diff line
@@ -5215,14 +5215,12 @@ static void si_enable_mc_ls(struct radeon_device *rdev, 


static void si_init_cg(struct radeon_device *rdev)

{

	bool has_uvd = true;



	si_enable_mgcg(rdev, true);

	si_enable_cgcg(rdev, true);

	si_enable_cgcg(rdev, false);

	/* disable MC LS on Tahiti */

	if (rdev->family == CHIP_TAHITI)

		si_enable_mc_ls(rdev, false);

	if (has_uvd) {

	if (rdev->has_uvd) {

		si_enable_uvd_mgcg(rdev, true);

		si_init_uvd_internal_cg(rdev);

	}
@@ -5230,9 +5228,7 @@ static void si_init_cg(struct radeon_device *rdev) 


static void si_fini_cg(struct radeon_device *rdev)

{

	bool has_uvd = true;



	if (has_uvd)

	if (rdev->has_uvd)

		si_enable_uvd_mgcg(rdev, false);

	si_enable_cgcg(rdev, false);

	si_enable_mgcg(rdev, false);
@@ -5241,11 +5237,11 @@ static void si_fini_cg(struct radeon_device *rdev) 
static void si_init_pg(struct radeon_device *rdev)

{

	bool has_pg = false;



#if 0

	/* only cape verde supports PG */

	if (rdev->family == CHIP_VERDE)

		has_pg = true;



#endif

	if (has_pg) {

		si_init_ao_cu_mask(rdev);

		si_init_dma_pg(rdev);

drivers/gpu/drm/radeon/si_dpm.c

+16 −18
Original line number Diff line number Diff line
@@ -37,8 +37,6 @@ 


#define SMC_RAM_END                 0x20000



#define DDR3_DRAM_ROWS              0x2000



#define SCLK_MIN_DEEPSLEEP_FREQ     1350



static const struct si_cac_config_reg cac_weights_tahiti[] =
@@ -1931,6 +1929,7 @@ static void si_initialize_powertune_defaults(struct radeon_device *rdev) 
			si_pi->cac_override = cac_override_pitcairn;

			si_pi->powertune_data = &powertune_data_pitcairn;

			si_pi->dte_data = dte_data_pitcairn;

			break;

		}

	} else if (rdev->family == CHIP_VERDE) {

		si_pi->lcac_config = lcac_cape_verde;
@@ -1941,6 +1940,7 @@ static void si_initialize_powertune_defaults(struct radeon_device *rdev) 
		case 0x683B:

		case 0x683F:

		case 0x6829:

		case 0x6835:

			si_pi->cac_weights = cac_weights_cape_verde_pro;

			si_pi->dte_data = dte_data_cape_verde;

			break;
@@ -2042,7 +2042,8 @@ static void si_initialize_powertune_defaults(struct radeon_device *rdev) 
	ni_pi->enable_sq_ramping = false;

	si_pi->enable_dte = false;



	if (si_pi->powertune_data->enable_powertune_by_default) {

	/* XXX: fix me */

	if (0/*si_pi->powertune_data->enable_powertune_by_default*/) {

		ni_pi->enable_power_containment= true;

		ni_pi->enable_cac = true;

		if (si_pi->dte_data.enable_dte_by_default) {
@@ -3237,10 +3238,10 @@ int si_dpm_force_performance_level(struct radeon_device *rdev, 
{

	struct radeon_ps *rps = rdev->pm.dpm.current_ps;

	struct ni_ps *ps = ni_get_ps(rps);

	u32 levels;

	u32 levels = ps->performance_level_count;



	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {

		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)

		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)

			return -EINVAL;



		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
@@ -3249,14 +3250,13 @@ int si_dpm_force_performance_level(struct radeon_device *rdev, 
		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)

			return -EINVAL;



		levels = ps->performance_level_count - 1;

		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)

		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)

			return -EINVAL;

	} else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {

		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)

			return -EINVAL;



		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)

		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)

			return -EINVAL;

	}
@@ -3620,8 +3620,12 @@ static void si_enable_display_gap(struct radeon_device *rdev) 
{

	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);



	tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);

	tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |

		DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));



	tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);

	tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |

	tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |

		DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));

	WREG32(CG_DISPLAY_GAP_CNTL, tmp);

}
@@ -4036,16 +4040,15 @@ static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 
static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,

					    u32 engine_clock)

{

	struct rv7xx_power_info *pi = rv770_get_pi(rdev);

	u32 dram_rows;

	u32 dram_refresh_rate;

	u32 mc_arb_rfsh_rate;

	u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;



	if (pi->mem_gddr5)

		dram_rows = 1 << (tmp + 10);

	if (tmp >= 4)

		dram_rows = 16384;

	else

		dram_rows = DDR3_DRAM_ROWS;

		dram_rows = 1 << (tmp + 10);



	dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);

	mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
@@ -6013,16 +6016,11 @@ int si_dpm_set_power_state(struct radeon_device *rdev) 
		return ret;

	}



#if 0

	/* XXX */

	ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);

	if (ret) {

		DRM_ERROR("si_dpm_force_performance_level failed\n");

		return ret;

	}

#else

	rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;

#endif



	return 0;

}