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Commit 75cc47bf authored by Ingrid Gallardo's avatar Ingrid Gallardo Committed by Gerrit - the friendly Code Review server
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drm/msm/sde: fix to set the interfaces for cont splash 



Current driver is not updating the correct interfaces
during the continuous splash case. Update the continuous
splash softwar to be able to read the interfaces enabled
for each controller.

Change-Id: I9318ee4434f1c59897aaaca499274287f8043f09
Signed-off-by: default avatarIngrid Gallardo <ingridg@codeaurora.org>
parent d57a1dd3

drivers/gpu/drm/msm/sde/sde_encoder.c

+11 −1
Original line number Diff line number Diff line
@@ -4828,7 +4828,7 @@ int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder) 
	struct sde_connector *sde_conn = NULL;

	struct sde_connector_state *sde_conn_state = NULL;

	struct drm_display_mode *drm_mode = NULL;

	struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter;

	struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;

	int ret = 0, i;



	if (!encoder) {
@@ -4965,6 +4965,16 @@ int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder) 
		phys->hw_ctl = (struct sde_hw_ctl *) ctl_iter.hw;

	}



	sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);

	for (i = 0; i < sde_enc->num_phys_encs; i++) {

		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];



		phys->hw_intf = NULL;

		if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))

			break;

		phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;

	}



	for (i = 0; i < sde_enc->num_phys_encs; i++) {

		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];

drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c

+9 −1
Original line number Diff line number Diff line
@@ -376,8 +376,16 @@ static void _sde_encoder_phys_cmd_setup_irq_hw_idx( 
{

	struct sde_encoder_irq *irq;



	if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_intf)

	if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl) {

		SDE_ERROR("invalid args %d %d\n", !phys_enc,

			phys_enc ? !phys_enc->hw_pp : 0);

		return;

	}



	if (phys_enc->has_intf_te && !phys_enc->hw_intf) {

		SDE_ERROR("invalid intf configuration\n");

		return;

	}



	irq = &phys_enc->irq[INTR_IDX_CTL_START];

	irq->hw_idx = phys_enc->hw_ctl->idx;

drivers/gpu/drm/msm/sde/sde_hw_ctl.c

+38 −0
Original line number Diff line number Diff line
@@ -576,6 +576,42 @@ static inline int sde_hw_ctl_trigger_flush_v1(struct sde_hw_ctl *ctx) 
	return 0;

}



static inline u32 sde_hw_ctl_get_intf_v1(struct sde_hw_ctl *ctx)

{

	struct sde_hw_blk_reg_map *c;

	u32 intf_active;



	if (!ctx) {

		pr_err("Invalid input argument\n");

		return 0;

	}



	c = &ctx->hw;

	intf_active = SDE_REG_READ(c, CTL_INTF_ACTIVE);



	return intf_active;

}



static inline u32 sde_hw_ctl_get_intf(struct sde_hw_ctl *ctx)

{

	struct sde_hw_blk_reg_map *c;

	u32 ctl_top;

	u32 intf_active = 0;



	if (!ctx) {

		pr_err("Invalid input argument\n");

		return 0;

	}



	c = &ctx->hw;

	ctl_top = SDE_REG_READ(c, CTL_TOP);



	intf_active = (ctl_top > 0) ?

		BIT(ctl_top - 1) : 0;



	return intf_active;

}



static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 timeout_us)

{

	struct sde_hw_blk_reg_map *c;
@@ -1011,6 +1047,7 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops, 
		ops->update_bitmask_merge3d =

			sde_hw_ctl_update_bitmask_merge3d_v1;

		ops->update_bitmask_cwb = sde_hw_ctl_update_bitmask_cwb_v1;

		ops->get_ctl_intf = sde_hw_ctl_get_intf_v1;

	} else {

		ops->update_pending_flush = sde_hw_ctl_update_pending_flush;

		ops->trigger_flush = sde_hw_ctl_trigger_flush;
@@ -1020,6 +1057,7 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops, 
		ops->update_bitmask_cdm = sde_hw_ctl_update_bitmask_cdm;

		ops->update_bitmask_wb = sde_hw_ctl_update_bitmask_wb;

		ops->update_bitmask_intf = sde_hw_ctl_update_bitmask_intf;

		ops->get_ctl_intf = sde_hw_ctl_get_intf;

	}

	ops->clear_pending_flush = sde_hw_ctl_clear_pending_flush;

	ops->get_pending_flush = sde_hw_ctl_get_pending_flush;

drivers/gpu/drm/msm/sde/sde_hw_ctl.h

+7 −0
Original line number Diff line number Diff line
@@ -380,6 +380,13 @@ struct sde_hw_ctl_ops { 
	 */

	u32 (*read_ctl_top)(struct sde_hw_ctl *ctx);



	/**

	 * get interfaces for the active CTL .

	 * @ctx		: ctl path ctx pointer

	 * @return	: bit mask with the active interfaces for the CTL

	 */

	u32 (*get_ctl_intf)(struct sde_hw_ctl *ctx);



	/**

	 * read CTL layers register value and return

	 * the data.

drivers/gpu/drm/msm/sde/sde_hw_mdss.h

+0 −8
Original line number Diff line number Diff line
@@ -561,19 +561,11 @@ struct sde_splash_lm_hw { 


/**

 * struct ctl_top - Struct contains CTL block properties

 * @value:	Store the CTL block register value

 * @mode_sel:	stores the mode selected in the CTL block

 * @dspp_sel:	stores the dspp selected in the CTL block

 * @pp_sel:	stores the pp selected in the CTL block

 * @intf_sel:	stores the intf selected in the CTL block

 * @lm:		Pointer to store the list of LMs in the CTL block

 * @ctl_lm_cnt:	stores the active number of MDSS "LM" blocks in the CTL block

 */

struct ctl_top {

	u32 value;

	u8 mode_sel;

	u8 dspp_sel;

	u8 pp_sel;

	u8 intf_sel;

	struct sde_splash_lm_hw lm[LM_MAX - LM_0];

	u8 ctl_lm_cnt;